Terrible Fire Accelerators

[chue]

I had a firmware mismatch issue with mine as well. For the TF530 board, I used the Dirty PCBs link from the MASTER branch of the TF530 repo.

When I used the firmware (dated 2017 March) from the same branch I got a black screen at bootup. I changed the firmware to the DEV version (RC2) and it booted.

[chue]

Also, the TF530 videos on YouTube are back online. They were offline for a bit.

https://www.youtube.com/channel/UCu4...y1ILAxNh7TGsmQ

[Anonymous32768]

Originally Posted by chue

I had a firmware mismatch issue with mine as well. For the TF530 board, I used the Dirty PCBs link from the MASTER branch of the TF530 repo.

When I used the firmware (dated 2017 March) from the same branch I got a black screen at bootup. I changed the firmware to the DEV version (RC2) and it booted.

Do you have a link to the location of the DEV firmware? I am having the same issue. Black screen.

[LADmachining]

Originally Posted by Anonymous32768

Do you have a link to the location of the DEV firmware? I am having the same issue. Black screen.

Towards the left side of the github page, there is 'Branch' drop-down box. Select 'Dev' here, then you can download the RC1 and RC2 binaries from the 'bin' folder.

Or try this: https://github.com/terriblefire/tf530/tree/dev/bin

[Cobe]

Originally Posted by supaduper

Yes just remove the Clock buffer jumper and the TF328 is disabled, you could make a fly lead like this so you donr have to keep opening the CD32

I just tried this and when I turn on cd32 without jumper screen stays black and power light dimmed.

[supaduper]

Originally Posted by Cobe

I just tried this and when I turn on cd32 without jumper screen stays black and power light dimmed.

then you have an early firmware , you need to update it if you have the programmer tools

[Cobe]

Ah..damn...
Thanks for prompt customer support!

[Pitka_Masa]

So how is it with thw tf328, are there differences in early and late CD32's? Mine is assembled in february 1994 and i was wondering if the tf328 works in it.

[supaduper]

Originally Posted by Pitka_Masa

So how is it with thw tf328, are there differences in early and late CD32's? Mine is assembled in february 1994 and i was wondering if the tf328 works in it.

In some some very early CD32`s there was a early rom version that can prevent the tf from working but yours will be fine ,there will no problem working with a TF328

[plasmab]

I've been digging through the Xilinx reports generated by the fitter. I then wrote some parsers in python to compare what I expected the pinouts to be vs what Xilinx set them as. There is a mismatch!!

TF530 Rev2

stephen@debiandev:~/git/tf530/build$ ./validate.py rev2 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 60 PIN: IPL<2> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: IPL<1> UCF: A<13> Error
Checking pin 57 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 UCF: A<13> PIN: IPL<1> Error
Parsing Pinfreeze File: work/ram_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 46 PIN: EXTINT UCF: Error - PIN NOT IN UCF FILE!

TF530 Rev3

stephen@debiandev:~/git/tf530/build$ ./validate.py rev3 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev3.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 34 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: DSACK<0> UCF: A<13> Error
Checking pin 43 UCF: A<13> PIN: DSACK<0> Error
Parsing Pinfreeze File: work/ram_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev3.ucf .... Done

[chue]

Does the pinout mismatch issue affect existing firmware (e.g. RC2), or is the issue only present in your unreleased firmware?

[8 Bit Dreams]

Originally Posted by chue

Does the pinout mismatch issue affect existing firmware (e.g. RC2), or is the issue only present in your unreleased firmware?

If i understand it correctly - it affects the card itself, as it is routed not like Xilinx expected to be.. Don't know is this causing instabilities though..

[plasmab]

Originally Posted by 8 Bit Dreams

If i understand it correctly - it affects the card itself, as it is routed not like Xilinx expected to be.. Don't know is this causing instabilities though..

It will affect all firmwares. I'll recompile them when i get a chance.

[Stedy]

Originally Posted by plasmab

I've been digging through the Xilinx reports generated by the fitter. I then wrote some parsers in python to compare what I expected the pinouts to be vs what Xilinx set them as. There is a mismatch!!

TF530 Rev2

stephen@debiandev:~/git/tf530/build$ ./validate.py rev2 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 60 PIN: IPL<2> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: IPL<1> UCF: A<13> Error
Checking pin 57 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 UCF: A<13> PIN: IPL<1> Error
Parsing Pinfreeze File: work/ram_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 46 PIN: EXTINT UCF: Error - PIN NOT IN UCF FILE!

TF530 Rev3

stephen@debiandev:~/git/tf530/build$ ./validate.py rev3 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev3.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 34 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: DSACK<0> UCF: A<13> Error
Checking pin 43 UCF: A<13> PIN: DSACK<0> Error
Parsing Pinfreeze File: work/ram_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev3.ucf .... Done

I checked the UCF files/schematic and fitter reports and found something else.

A13 is an unused input and was optimised out by the fitter.
IPL1/2 connect from the 68000 socket to the 68030, not to the CPLD. I removed them.

Comparing the Rev 2 UCF aginast Rev3 and the schematic, I saw the following errors

Signal   Rev 2 pin     Rev 3 pin  Schematic
AVEC    35                63           35
DSACK0 63             MIA         63
FC0       34               40           34
FC1       33               35           33

After making those edits and adding a timing constraint on the clock from the V2 file, I rebuilt the design and checked the fitter reports against the schematic. Attached is a JEDEC file to program the board, new UCF file, ISE project file and the Verilog source. Can someone try the attached image and report their findings?

Ian

[plasmab]

My worry with removing them from the UCF file is that they can get set as ground pins randomly by ISE :/

[8 Bit Dreams]

known working update from Poland
it's 534
https://www.ppa.pl/graffiti/obrazek/...0-4mb-fast-ram

[TimT]

Could someone look at these voltages for me? this will fail " initialize jtag chain " the 68000 socket pins are not soldered in yet I tested the board without the pins. I am using a bench power supply. did not get anything at C2. Thanks

[8 Bit Dreams]

Originally Posted by TimT

Could someone look at these voltages for me? this will fail " initialize jtag chain " the 68000 socket pins are not soldered in yet I tested the board without the pins. I am using a bench power supply. did not get anything at C2. Thanks

1. as for me - it looks like tiny short at the resistor array beneath FPU socket. Take a microscope and have a check
2. You need both CPLD's to be able to program them...

[TimT]

I checked the resistor's, all seem good. I did a " hot pull " of a CLPD and soldered it in. Now it will initialize chain, but can't program them. I did try the bus CLPD only but got errors. I ordered more CLPD'S.. Sorry can't rotate the image.

[TimT]

8 Bit Dreams what soldering tip are you using on the Caps ect..? I am just getting to much solder on the joints. also is there anything better then Alcohol to clean the boards?
Thanks