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Old 12 February 2019, 11:30   #461
bytestorm
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Floppy disk

Quote:
Originally Posted by majinga View Post
Depends on the KS version.
With KS 1.2, you can have 1 MB chip + 1MB slow.
With KS 1.3 or higher, 1 MB chip + 1.5 slow
Ok, but changing the KS is just to burn a new eprom with the korrect kick right?

Anything else i need to consider?

Chipmem 1MB
Slowmem 1.5MB
Fastram?
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Old 12 February 2019, 11:48   #462
majinga
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whdload definitely requires some fast RAM. And an HDD.

To use EPROMs as KS you may have to mod the board:
http://eab.abime.net/showthread.php?t=82824

Or use a KS switcher that take care of that.
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Old 12 February 2019, 12:27   #463
bytestorm
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Quote:
Originally Posted by majinga View Post
whdload definitely requires some fast RAM. And an HDD.

To use EPROMs as KS you may have to mod the board:
http://eab.abime.net/showthread.php?t=82824

Or use a KS switcher that take care of that.
hmm.. and fast ram would be using a accelerator like ACA500plus or Wicher 500i I guess?
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Old 12 February 2019, 12:58   #464
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Yes, or Terrible Fire or other accelerators. There are many accelerators for fast ram and IDE.
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Old 12 February 2019, 13:07   #465
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Without swapping the Agnus you would be limited to 512K chip, not 1MB. For that, you really do have to swap the 8371 for a 8372A. Other than that the rev 5 can be made to perform much like the rev 6A.
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Old 12 February 2019, 13:14   #466
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hmm why didnt I research a bit more before buying 2 amiga 500s.. both ended up being rev 5 hahaha.. never thought it would be THAT big difference. Could have just bought 1 500 plus for the money straight away instead of a upgrademarathon
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Old 12 February 2019, 13:21   #467
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Quote:
Originally Posted by Tahoe View Post
Without swapping the Agnus you would be limited to 512K chip, not 1MB. For that, you really do have to swap the 8371 for a 8372A. Other than that the rev 5 can be made to perform much like the rev 6A.

Ah, true! Sorry my bad.

With this expansion board and the agnus 8371 is possible to have:

512k slow without the Gary Adapter
1M slow with the Gary Adapter
1.5M slow with the Gary Adapter ans KS >= 1.3

and only 512k of chip


- 512k slow OK
- 1M slow OK (Con Gary Adapter)
- 1.5M slow OK (Con Gary Adapter)
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Old 13 February 2019, 15:17   #468
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Well, I bought 2x 8372A agnuses now . Now I'll see how to make/source a couple of these kits!
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Old 23 February 2019, 01:00   #469
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Quote:
Originally Posted by PeteAU View Post
Hi patzik,

I'm trying to help you out to avoid wasting boards/money on this:
- You used a different CAM file, so the ground plane changed. The margins are too tight in a few places. Look at the grounds for U1, they look a bit shitty. I had a CAM file in my original ZIP, use that.
- The trace you added near U3 blocks off the ground to the chip - it won't work.
- The trace you added for switch 3rd pin blocks the short path for ground to U2/U3 - I don't think this is very good.

If you want to do something useful, remove the jumpers for U1/U3/U4 entirely. That would simplify things and avoid confusion. Removing the pre-links is retrograde IMO. Then I would rename to jumper above U2 to say something like "A500+ (left) / A500 (right)".
I made a new version, only thing changed is the added mouse bites for easier separation of the boards, could you please check these gerbers?
Attached Files
File Type: zip Test Mousebites.zip (638.7 KB, 45 views)
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Old 23 February 2019, 09:08   #470
SukkoPera
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Quote:
Originally Posted by bytestorm View Post
btw, any DIY kits of the latest version availible for sale?
I have a couple of kits left for sale on AmiBay if you are still interested.
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Old 29 March 2019, 16:53   #471
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Hello guys.

I like to show you my version of gary adapter pcb. For few reasons I move jumpers to other side.
I had read the thread, and i cannot see one option. I have A500 with Rev6 PCB, and i have 1MB chips onboard, setted to 1MB chip.

I like to make trapdoor PCB witch max memory possible, and use all memory onboard. But how to set jumpers in my case? When i have 1MB onboard, there is J2 switched to down position. So there is nescesary to wire JP2 - RAS_CTL, or I have to make some diffrent wiring?
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Old 31 March 2019, 08:10   #472
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Quote:
Originally Posted by adambyw View Post
I had read the thread, and i cannot see one option. I have A500 with Rev6 PCB, and i have 1MB chips onboard, setted to 1MB chip.
You have put extra DIP DRAMs onto the motherboard? Unfortunately, it won't work with this board. IIRC - my memory is vague - it won't be able to split out the second RAS (RAS1) and thus fail. Your only choice is to remove them and go back to a stock motherboard.
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Old 31 March 2019, 08:58   #473
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Quote:
Originally Posted by adambyw View Post
Hello guys.

I like to show you my version of gary adapter pcb. For few reasons I move jumpers to other side.
I had read the thread, and i cannot see one option. I have A500 with Rev6 PCB, and i have 1MB chips onboard, setted to 1MB chip.

I like to make trapdoor PCB witch max memory possible, and use all memory onboard. But how to set jumpers in my case? When i have 1MB onboard, there is J2 switched to down position. So there is nescesary to wire JP2 - RAS_CTL, or I have to make some diffrent wiring?
Did the board pass DRC? It seems like the ground pins of U3 and U4 are not connected. Also (my personal pet peeve ), don't intersect your groundplane too much. Now, your ground connection between the ic's and the decoupling cap is very long making the caps less effective.
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Old 01 April 2019, 11:13   #474
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@PeteAU
Yes, i have extra DIP's onboard. And also have typical 0,5mb trapdoor with RTC. This is how I bought it, so i thought it was possible to set onboard as 1MB chip and trap as 0,5 slow.
While searching i found ReSlow mod by Pekka Pessi. http://netti.nic.fi/~pii/
In oryginal mod it was'n gentle solution, maked on prototype pcb's, and also lot of wires. I want to pimp my Amiga, but keep it oryginal as possible. This mod can be maked as small pcb under U35, with additional 4 cables to chips' as I prepared: https://easyeda.com/editor#id=|8d89d...f3a5da6275f863

@Mathesar
Yes, it pass DRC. But for unknown reason program changed net name from GND to U3_7 and U4_7. I also added a few GND vias, hope will be better.
Thanks for vigilance
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Old 03 April 2019, 18:32   #475
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Hi Pete - quick question, on those SOJ-42 packages, there's Address lines A0 to A9 - 10 in total - when only A0 to A8 are available - are you just going NC on A9 on the IC, or is it tied to A8?
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