CoZe's Scandoubler Project - Help needed !

[coze]

Hello dear EAB members,
After some time (quite some time that is ) I decided to start my scandoubler project which I got some preliminary infromation in this thread. I decided using an FPGA is overkill indeed and LordV's A600 8mb RAM project pointed me in the CPLD direction, which I think is just the right size ! I also stumbled upon Terasic's Max Micro kit which looks like a perfect development platform for such a project. It houses a EPM2210F324 CPLD, which can house 2210 logic elements and has 272 IO pins. Max Micro development board itself has 88 IO pins, I guess the rest are used for configuring the device. Anyway, I think 88 IOs are quite adequate for this project.

Max Micro User Manual

Anyway, firstly I'ld like start building an ECS scandoubler with no interlace support (baby steps). I will interface Max Micro directly to Denise, pull TTL RGB signals and clocks from there, and send them to DACs at double frequency. I bought a DAC0832LCN for this purpose, which is a 8 bit DAC.

I have lots of questions about the electrical compliance of such a project though. First, the altera CPLD is a 3.3v device. Will it work ok with 5v TTL signals of denise ? I searched altera forums and came across some discussions but it was about the cyclone device (which is an FPGA). As far as I can see, LordV didn't do anything about it in his project and his CPLD was able to handle 5v TTL signals from the 68000 ? Do I need to worry about this or can I connect denise outputs to CPLD directly ?

Also I have a similar question about the DAC I'm using. The datasheet says it's compatible with TTL signals with 1.4V threshold. Will this be ok to interface it directly with the CPLD ? Also, will the output be VGA compatible ? I read that the VGA analog signal is 0v-0.7v. Will this DAC produce an analog signal in that range ? Or do I need to do something to pull it to that range ?

And finally, I have some questions about the clocks. I checked Dennis's amber code from Minimig sources. He has nice lo-res pixel clocks and VGA clocks. How do I get these from the Denise ? I checked Denise pinouts and I have; CCK, _CSYNC, _CDAC, 7MHz_A signals. The Amiga Technical Reference manual says about these,

7MHz : This is the 7.16 MHz system clock
CDAC : This is a 7.16 MHz clock that leads the 7.16 MHz system clock by 70 ns (90 degrees)
C3 Clock : For NTSC, this is a 3.58 MHz clock that's synced to the rising edge of the 7.16MHz system clock. Also known as CCKQ in some places. For a PAL system, this is 3.55 MHz.
The CSYNC is composite sync most probably, which becomes low after each scanline. Though I'm at a loss at this moment as how does this relate to seperate HSYNC and VSYNC (Minimig amber code uses them seperately)

So, somehow I should get a clock (pixel clock ?) to sample the Denise outputs from these but I have no idea.

Denise pinouts :

Basicly I'm trying to duplicate an ICD FlickerFixer which sits on Denise socket. It does everything with just signals from the Denise socket, so it must be possible.

About future expandability of the project, Dennis seems to have implemented a linebuffer for laced modes. I don't know if this will fit into the CPLD (I hope so) if it does, I may pull off support for interlaced modes without having to interface the CPLD with some sort of static RAM, which will be cool.

For AGA compatibility I think I just need to add more I/O lines. DACs are already 8 bit. Have to double the size line buffer for interlaced modes, but I really don't worry about it right now there's quite a bit of time I get into that stage.

[Toni Wilen]

Superhires: main system clock (~28MHZ, 35ns pixel clock), hires = half of main clock (~14MHz, 70ns), lores = 1/4 of main system clock (~7MHz, 140ns)

Denise internally generates other pixel clocks using 7MHz/CDAC/C3 signals.

Note that you can't know Denise's current pixel clock (lores/hires/shres) without peeking the bus.

Hope this random information helped

[keropi]

I bet alexh will add to this thread...

[coze]

Thank you Toni, yes it was helpful Damn it gets much more complicated than I thought ... Ok, I'll just stick to lores now and use the 7MHz signal. Just enough to get to see the kickstart screen later I'll have to find a way to determine denise pixel clock changes. this is really strange. I mean Denise produces RGB TTL signals, and these should be changed into analog somewhere (something called the Video Hybrid does this) for the RGB port. how does the Video Hybrid do it without the pixel clock ? It only receives RGB TTL and CSYNC. What exactly is CSYNC ?

On another note, the CPLD used by LordV was EPM3064 which turns out to be 5v compatible . It seems I need some pull down resistors to interface my EPM2210.

[Toni Wilen]

I think the DAC does not need any clocks and CSYNC-pin (which is HSYNC+VSYNC combined) is only related to COMP-pin that is not connected on A500.

Hmm.. Denise has pins marked PIXELSW which may have something to do with pixel clock. (or perhaps not)..

Time to play with logic analyzer

[coze]

PixelSW (according to Amiga Technical Reference manual ) is pixel switch, background color indicator (color 0), on a pixel by pixel basis.

[Toni Wilen]

Originally Posted by coze

PixelSW (according to Amiga Technical Reference manual ) is pixel switch, background color indicator (color 0), on a pixel by pixel basis.

Ah, of course, genlock needs that information.

[Misha]

Anyway, firstly I'ld like start building an ECS scandoubler with no interlace support (baby steps). I will interface Max Micro directly to Denise, pull TTL RGB signals and clocks from there, and send them to DACs at double frequency. I bought a DAC0832LCN for this purpose, which is a 8 bit DAC.

@Coze

If your successful be sure to send me a PM as i`d have one of these off you (for cash ofcourse ) infact i might have half a dozen for future projects you understand! i know i could always make my own but i`d rather someone else do the hardwork,as i`m not a tinkerer i wouldn`t want to risk f**king everything up.

[coze]

Thanks !

I found some information as to how to interface a 3.3v device to 5v device here. It seems I'll have to use 90 ohms transistors on every signal coming from denise. For this prototype it's ok, but in the future I'll use a 5v compatible CPLD as LordV.

It seems DAC will be ok with 3.3v outputs from the CPLD as it's above 2.4v threshold for 5v devices. But I still don't have any idea how I'll have a 0-0.7v signal from the DAC. It seems I have to supply the DAC with Vref, and I guess that has something to do with the output levels, but the equations at the datasheet don't make sense to me at the moment.

[Zetr0]

@coze

i have a few cpld's that are 5v and 5v signal tollerant, what size / type you looking for... if i have them i will send you a couple dont worry about the cost i got a fair few cheap.

(i am making a postal run tomorrow so shout now) i have yet to post anything to japan

[coze]

Aaah, thanks Zetro for the offer But this kit already has it's programmer/software bundled, so I'ld like to use this if possible. It has a great design utility called quartus, and you just need to plug the USB cable and off you go (no messing with parallel port and stuff). In fact I have some basic binary clock and binary adder running on it already and it's quite sweet If I get some CPLD from you I'll have to find/build programmer/software to program those devices which could set me back ... (well eventually it will happen when I move to a 5v CPLD though )

[Mick_AKA]

coze will of course be mass producing these for all EAB members yes?

[alexh]

Originally Posted by coze

Have to double the size line buffer for interlaced modes

If you're going to deinterlace you need a MUCH bigger buffer. You need to store all the lines of the previous field.

To get a good result you also need a digital filter but I doubt the ICD Flicker Fixer had one.

[alexh]

http://www.actel.com/documents/APA_5V_AN.pdf

[coze]

Originally Posted by alexh

If you're going to deinterlace you need a MUCH bigger buffer. You need to store all the lines of the previous field.

Yes, I know I have to buffer the whole frame. What I wanted to mean there is the frame buffer of an AGA mode would be double the size of ECS mode.

[alexh]

Sorry. My mistake. I thought that you were just going to scandouble first. The memory for that is of course much lower as you only have to buffer a little over one line as opposed to one field.

[coze]

Originally Posted by Mick_AKA

coze will of course be mass producing these for all EAB members yes?

of course I will, if I can get one to work that is

[Oli_HD]

Ive been working on a broken scan doubler for an a.org member I know and unfortunatly it ment I virtually had to reverse engineer the darn design.
It outputs a 31kz signal just fine but its a single colour, the colour of the first line of the screen, but anyway I woner off topic.

The card clips over Lisa (AGA) and takes the 28Mhz signal, halves it and runs to some fifo memory, it clocks the RGB in at 14Mhz and reads it out at 28Mhz, as its getting the digital in it only uses a DAC. (a standard VP/BT101, like the Amiga uses) The CPLD doesnt seem to do much at all other than that clock reduction and doubling of the Hsync signal (counted in reference to the 28Mhz clock then halved maybe?)

Dont even think about using a CPLD as a FIFO, with its NAND gate design it would need about 5000 microcells or something silly like that.
Try compiling the Minimigs scandoubler code, you couldnt use it but Dennis built the line buffer into the FPGA so would show you just how big a CPLD you would need.

What is a much (much much) better option is to just buy a AL251 scan doubler chip and wire it up to the digital signals and you are done.
For OCS/ECS thats fine, its 16bit. Use FIFO memory would let you do 24bit though.

Have fun!

[Stedy]

Coze,

A few hints. For the 5 to 3.3V conversions, look for a 74LV245, or similar logic device. This is an 8 bit wide data buffer that operates off 3.3V but is 5V tolerant.

The DAC0832 D/A converter is not suitable. It has a settling time of 1us or throughput of 1MHz. Typically when working with Video signals, you use 27 or 54MHz parts (2x and 4x pixel clock). Look at the Analog Devices ADV7120 for an idea or two. As most fast D/A converters are current mode, you typically add a 37.5 ohm load to convert current to volts and allow you to drive 75 ohm cables.

You may also need to consider video buffer amplifiers for driving the VGA cable.

Likewise, to sample the RGB video, you need a fast ADC or use a video decoder. The Analog Devices ADV7401 accepts RGB, Y/C or CVBS video and outputs the sampled video data as RGB 4:4:4 data.

If you want to use the Averlogic AL251, you need a video decoder like the ADV7401 or the SAA7118 or the S5D0127. These parts accept Y/C, CVBS and on the SAA7118, RGB video. Make sure the digital data is output in the right form.

I hope this gives you a few pointers in the right direction.

Ian

[alexh]

Originally Posted by Stedy

Likewise, to sample the RGB video, you need a fast ADC or use a video decoder. The Analog Devices ADV7401 accepts RGB, Y/C or CVBS video and outputs the sampled video data as RGB 4:4:4 data.

If you want to use the Averlogic AL251, you need a video decoder like the ADV7401 or the SAA7118 or the S5D0127. These parts accept Y/C, CVBS and on the SAA7118, RGB video. Make sure the digital data is output in the right form.

The output from the Amiga Denise or Lisa chips is digital RGB video not analog. No need for any ADC's