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Old 06 July 2020, 21:18   #321
kipper2k
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for those who missed the first portion of the thread you can read the Amiga FPGA links here on Mikes blog ...

https://www.mike-stirling.com/

It will bring you up to speed pretty quick.

(The price for this is expected to be ~200 euros. final specs still to be finalized

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Originally Posted by digiflip View Post
where is the mkstr store? I need to get on the preorder list pronto
mkstr lives in the UK

Last edited by kipper2k; 06 July 2020 at 21:23.
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Old 06 July 2020, 22:15   #322
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Thanks for the useful explanation robinsonb5
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Old 06 July 2020, 22:19   #323
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Quote:
Originally Posted by kipper2k View Post
(The price for this is expected to be ~200 euros. final specs still to be finalized
Wow
Now I am really thinking of selling my Aca 500+ (that serves me great, don't get me wrong), and upgrading to this.
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Old 07 July 2020, 10:53   #324
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Very nice, can you say anything about the SD drive speed? I know earlier in the thread you talked about a 4-bit SDIO controller being implemented eventually possibly even with DMA. That sounds really promising.

Are you guys aware of the Atari "suska" project? He has implemented a full 030 with instruction set, addressing modes, MMU, cache, pipelined architecture. Called 68K30 but not released publicly, but the 68K30L without MMU is available Open Source under a cern ohl v1.2 license. Also 68000 and 68010 has been implemented as well as many of the Atari custom chips, very impressive.

I wonder how the 68K30L fairs in comparison to TG68 if it would be used in an Amiga?

https://download.experiment-s.de/Configware/

Latest release notes:
https://download.experiment-s.de/Con...leasenotes.txt

This below is taken from the release notes from an earlier version, dec 2015, apparently a fpu 68882 and an 040 is worked on as well, I don't know the status there:

There are two of those ip cores...
One is a fully featured complex instruction set computer (CISC) CPU with 68030 instruction set, addressing modes, memory management unit, instruction and data cache and the coprocessor interface. It is developed in a pipelined architecture. The shifter unit is designed as a barrel shifter with one clock cycle delay. This is the 68K30 version. I will not release this CPU in the near future. Interested people can contact me concerning this IP core.

The other version is a subset of the 68K30 called 68K30L. This ip core features all addressing modes and instructions but does not have MMU, cache and coprocessor interface. The shifter unit is modeled as a convetional shift register with several clock cycles delay. The 68K30F IP core which will implement the 68882 floating point unit seamlessly to the 68K30. This work is in progress. The 68K40 IP core featuring a MC68040 compatible machine.
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Old 07 July 2020, 12:44   #325
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I have no updated numbers for the SD card at the moment (that part isn't ported to the new FPGA yet). The interface is indeed 4-bit and there is a block-based dedicated cache, but it's definitely still a bit hobbled by being PIO-only via the Gayle emulation.

There is no reason it couldn't support DMA into fastmem, given a suitable driver, and this will almost certainly be implemented at some point. I won't hold up the release for it though - it will be dealt with as a firmware update (the board is going to be field upgradable).

Mike
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Old 07 July 2020, 16:58   #326
jbilander
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Thanks for the update anyway. Sounds promising. Imagine eventually having this core put on a chip and clock the bejesus out of it, it would be in "Phone Me Now!" territory pretty easily This can now be realised, fab for free (130nm process, 100pcs) by Google as long as it's open source. Might be worth looking at...

https://www.theregister.com/2020/07/...chip_hardware/

https://hackaday.com/2020/06/30/your...wafer-in-2020/
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Old 07 July 2020, 17:16   #327
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Quote:
Originally Posted by jbilander View Post
Thanks for the update anyway. Sounds promising. Imagine eventually having this core put on a chip and clock the bejesus out of it, it would be in "Phone Me Now!" territory pretty easily This can now be realised, fab for free (130nm process, 100pcs) by Google as long as it's open source. Might be worth looking at...

https://www.theregister.com/2020/07/...chip_hardware/

https://hackaday.com/2020/06/30/your...wafer-in-2020/
Nice, looks like google (skynet) is after peoples IP's by sweetening the pot. You know full well they aren't doing this out of the goodness of their heart lol. The TG68 core is open source anyway (and has not been modified by Mike.

edit... so this is pretty sneaky... it gets people to reelase their code, and then they aren't even guaranteed a slot, and there aren't that many slots

Last edited by kipper2k; 07 July 2020 at 17:46.
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Old 07 July 2020, 17:55   #328
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"Don't be evil" is their slogan, right?, Skywater not Skynet Yeah of course they want to see what comes out of this and they probably don't know what to do with that old Minnesota fab anyway. However, If you haven't modified the TG68, I cannot see you are in any risk here if you're making it an ASIC down the line, but I haven't read the fine-print, if it goes beyond the CPU HDL being open sourced or not, maybe other stuff such as controllers and glue logic can be put in a CPLD.
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Old 07 July 2020, 18:00   #329
kipper2k
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Quote:
Originally Posted by jbilander View Post
"Don't be evil" is their slogan, right?, Skywater not Skynet Yeah of course they want to see what comes out of this and they probably don't know what to do with that old Minnesota fab anyway. However, If you haven't modified the TG68, I cannot see you are in any risk here if you're making it an ASIC down the line, but I haven't read the fine-print, if it goes beyond the CPU HDL being open sourced or not, maybe other stuff such as controllers and glue logic can be put in a CPLD.

Another thing is, lets suppose you are selected for the 100 chips, once they are spoken for how much would it cost to actually get more fabricated. if you commit your HW design to accept a custom ASIC then you need to know these answers in advance

edit, apparently there is a 40 pin I/O limit so i think anything Amiga is pretty well toast

Last edited by kipper2k; 07 July 2020 at 18:07.
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Old 07 July 2020, 18:09   #330
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Yes that is true, you'll need to have it written in ink before committing to such a design. How much it will cost to order another batch of 100 pcs for example.
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Old 07 July 2020, 18:19   #331
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I think the Amiga will be well served by this accel .
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Old 14 July 2020, 03:18   #332
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Originally Posted by jbilander View Post
Very nice, can you say anything about the SD drive speed? I know earlier in the thread you talked about a 4-bit SDIO controller being implemented eventually possibly even with DMA. That sounds really promising.

Are you guys aware of the Atari "suska" project? He has implemented a full 030 with instruction set, addressing modes, MMU, cache, pipelined architecture. Called 68K30 but not released publicly, but the 68K30L without MMU is available Open Source under a cern ohl v1.2 license. Also 68000 and 68010 has been implemented as well as many of the Atari custom chips, very impressive.

I wonder how the 68K30L fairs in comparison to TG68 if it would be used in an Amiga?

https://download.experiment-s.de/Configware/

Latest release notes:
https://download.experiment-s.de/Con...leasenotes.txt

This below is taken from the release notes from an earlier version, dec 2015, apparently a fpu 68882 and an 040 is worked on as well, I don't know the status there:

There are two of those ip cores...
One is a fully featured complex instruction set computer (CISC) CPU with 68030 instruction set, addressing modes, memory management unit, instruction and data cache and the coprocessor interface. It is developed in a pipelined architecture. The shifter unit is designed as a barrel shifter with one clock cycle delay. This is the 68K30 version. I will not release this CPU in the near future. Interested people can contact me concerning this IP core.

The other version is a subset of the 68K30 called 68K30L. This ip core features all addressing modes and instructions but does not have MMU, cache and coprocessor interface. The shifter unit is modeled as a convetional shift register with several clock cycles delay. The 68K30F IP core which will implement the 68882 floating point unit seamlessly to the 68K30. This work is in progress. The 68K40 IP core featuring a MC68040 compatible machine.
I've heard about at least 2 people trying to adapt this one to minimig, and both of them gave up.
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Old 14 July 2020, 19:03   #333
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just wondered if any news or if preorder is going up soon?
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Old 14 July 2020, 20:04   #334
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Working on the A500/1000/2000 version PCB layout at the moment - it's a dense board so a bit slow going, but progressing. This version should also work with kipper2k's A600 adapter. A1200 version will follow at some point after release.
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Old 22 July 2020, 11:23   #335
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Interesting project.

I've not read the source code for TG68k.C so forgive me if I'm completely wrong, but I thought that the TG68k.C internally is not a re-implementation of the architecture of any existing 68k CPU? It is not a microcoded CPU nor does it pretend to be one (like FX68k). It is binary compatible, register compatible, stack frame compatible etc. but under the hood completely different.

The speed improvements over the original 68k series (for a given clock speed) I would imagine comes from a reduction in instruction fetch, data fetch, instruction decode and most importantly instruction execution time? Arithmetic instructions probably execute in vastly reduced cycles, particularly multiply and divide.

I believe TG68k is a very simple implementation and does not have a multi-stage pipeline architecture with writeback, instruction cache, data cache, branch prediction etc. which is where the real architectural performance comes from. All of which can be added over time.

From what I've read Mike has added an instruction cache, I'd be interested to understand what type of cache he added (direct mapped? 4 way set associative?) where it was placed and how it is invalidated (writeback). I guess it is not an external cache similar to the one in a MegaSTe? That is usually considered a mixed cache?

Looking forward to seeing how this progresses.
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Old 27 July 2020, 13:01   #336
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Quote:
Originally Posted by mkstr View Post
Working on the A500/1000/2000 version PCB layout at the moment - it's a dense board so a bit slow going, but progressing. This version should also work with kipper2k's A600 adapter. A1200 version will follow at some point after release.
No big issue whether this is possible or not but could you still use existing CF hard drives on the IDE with the new accelerator? Or must you use the SD card slot? This has got my mouth watering! Fantastic work Mike
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Old 28 July 2020, 14:50   #337
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@alexh: I will give some details on the cache architecture once released. I'm actually trying some different approaches at the moment to see if I can get any more performance out, particularly in overcoming DRAM latency.

@rabidgerry: The internal Gayle emulation would conflict with a motherboard Gayle (I actually think it will just override it altogether, so on a 600 the accelerator's SD card will probably work and the PCMCIA and on-board IDE will not). There will be some way to inhibit the emulated Gayle though, either through a flash configuration option or with a jumper.

Mike
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Old 28 July 2020, 17:19   #338
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Wink

@mkstr
Will this work on a CD32?
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Old 28 July 2020, 19:32   #339
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I think the CD32 version will be awesome, and A4000
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Old 10 August 2020, 19:57   #340
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Nice project. Got some Xilinx boards from QMTECH today. If I ever manage to get it working with TG68 in A500 rev 6A I maybe experiment more with LiteSATA or maybe scandoubler capabilities with hdmi out. I hope your project succeed so I'll have push in the right direction as well!
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