English Amiga Board


Go Back   English Amiga Board > Requests > request.UAE Wishlist

 
 
Thread Tools
Old 08 August 2007, 20:29   #21
demoniac
Registered User
 
Join Date: Jul 2005
Location: -
Posts: 1,441
Excellent findings. To me this is one step closer to recreating the Amiga prototype with breadboards.
demoniac is offline  
Old 21 May 2008, 16:39   #22
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,691
New logic analyzer findings (it has been too long..)

I finally decided to snoop RGA (custom register address bus) bus. Should have done this ages ago but I was stupid and too lazy

RGA = custom address accessed, WE = write enable, INT3 = Agnus int3 pin, DMAL = Paula DMAL pin (not used yet), IPL = CPU interrupt level.

Guess whats happening in these images? (hint in image names)

Apparently every custom chip number is directly available in RGA bus, even if it is Agnus internal register. (RGA is used to transfer data to/from Denise and Paula, for example Agnus bitplane DMA puts BPLxDAT to RGA and does DMA from chipram)

This means blitter line mode cycle diagram mystery will be finally solved in few days.

EDIT: delay between bltsize and first DMA transfer looks interesting and is quite long..
Attached Thumbnails
Click image for larger version

Name:	blit_d.png
Views:	405
Size:	88.8 KB
ID:	16646   Click image for larger version

Name:	blit_bcd.png
Views:	310
Size:	89.0 KB
ID:	16647   Click image for larger version

Name:	blit_abcd.png
Views:	309
Size:	89.2 KB
ID:	16648  

Last edited by Toni Wilen; 21 May 2008 at 18:35.
Toni Wilen is offline  
Old 23 May 2008, 14:31   #23
sink
Registered User
 
Join Date: Jan 2006
Location: france
Age: 50
Posts: 191
toni u are a god! thk for your time, patience and devotion about "I think this explains problems with demos with vector objects because WinUAE's linedraw uses too many cycles depending on line type.. (testing soon)", you think that can be a solution for this probleme for exemple demos of virtual dream in the middle we can see that (the rest work like a charm):
Attached Thumbnails
Click image for larger version

Name:	VD-tsunamiDemo_001.png
Views:	341
Size:	27.7 KB
ID:	16662  
sink is offline  
Old 23 May 2008, 16:09   #24
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,691
Line draw mode was boring, didn't find anything interesting

It is -C-D-C-D-C-D except write is free cycle when in onedot mode and no pixel needs to be drawn. (nothing new here)

3 free cycles between write to BLTSIZE and first blit cycle are also free (this isn't exactly emulated yet) but this can't fix above demo either..

ADDED: I guess copper and blitter cycles don't align properly causing lost cycles (demo writes blitter registers using copper)

Last edited by Toni Wilen; 23 May 2008 at 16:33.
Toni Wilen is offline  
Old 24 May 2008, 07:48   #25
sink
Registered User
 
Join Date: Jan 2006
Location: france
Age: 50
Posts: 191
oki thk for this info , like i'm a a500 maniak , please continue your work about the 500
sink is offline  
Old 15 July 2008, 03:05   #26
boing_1000
A1000 Addict
boing_1000's Avatar
 
Join Date: Jan 2006
Location: Eastern USA
Age: 34
Posts: 560
Toni you work some mysterious magic

A logic analyzer, though...haha I admire your dedication.
boing_1000 is offline  
Old 18 March 2021, 17:23   #27
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,691
Yes, necropost but on mostly on topic

Logic analyzer upgrade. After almost 14 years later.. DSLogic U3Pro32. Still to do: scope upgrade. Possibly Siglent SDS2104X Plus.

Main reason was much larger internal RAM (enough space for dozens of frames), much more than Logicport which barely had enough memory for single scanline. (2k samples@32 channels vs 2G divided by number of channels without RLE compression)

Software is also much faster and supports programmable (in Python) decoders. Screen capture shows quickly made RGA to register names decoder. (No, I don't remember all register numbers!)

Data bus uses generic "Parallel" decoder which I only modified to support 16-bits (original only supports up to 8). "AmigaRGA" is also based on "Parallel".

Oddly enough software does not have built-in signal grouping support so you have to use existing decoders or write your own to get useful output.
Attached Thumbnails
Click image for larger version

Name:	dslogica500.jpg
Views:	92
Size:	433.2 KB
ID:	71330   Click image for larger version

Name:	dslogic.png
Views:	79
Size:	36.3 KB
ID:	71331  

Last edited by Toni Wilen; 18 March 2021 at 18:37. Reason: name fixed
Toni Wilen is offline  
Old 18 March 2021, 18:36   #28
Exodous
Registered User

 
Join Date: Sep 2019
Location: Leicester / England
Posts: 113
Smile Toni breaks Google

I've been looking for a logic probe recently and so I Googled the following - no quotes etc. just what is typed below:
DSLogic U32Pro32
Google comes back with no results at all. I can't ever remember seeing that!

Did you mean the U3Pro32?
Exodous is offline  
Old 18 March 2021, 18:44   #29
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,691
Fixed
Toni Wilen is offline  
Old 25 March 2021, 13:04   #30
Daedalus
Registered User

Daedalus's Avatar
 
Join Date: Jun 2009
Location: Dublin, then Glasgow
Posts: 5,148
I use an earlier analyser from DSLogic, and it's great. I'm using the Sigrok software with it instead though, and it allows grouping of signals. It might be worth checking out Sigrok as an alternative. (Incidentally, the DSView software is based on Sigrok sources but with some changes to the UI.)
Daedalus is offline  
Old 25 March 2021, 15:26   #31
Toni Wilen
WinUAE developer
 
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 46
Posts: 24,691
Quote:
Originally Posted by Daedalus View Post
I use an earlier analyser from DSLogic, and it's great. I'm using the Sigrok software with it instead though, and it allows grouping of signals. It might be worth checking out Sigrok as an alternative. (Incidentally, the DSView software is based on Sigrok sources but with some changes to the UI.)
U3Pro versions are not (yet?) supported by Sigrok software. But it does not really matter, custom decoder fixes the problem better than grouping
Toni Wilen is offline  
 


Currently Active Users Viewing This Thread: 1 (0 members and 1 guests)
 
Thread Tools

Similar Threads
Thread Thread Starter Forum Replies Last Post
logic analyzer function Rock'n Roll request.UAE Wishlist 1 25 August 2018 14:41
Logic Analyzer for Amiga motherboard repair majsta Hardware mods 0 21 September 2012 21:31
Logic Analyzer on an A500 RedskullDC support.Hardware 2 13 November 2009 09:06
Logic Analyzer ??????? Dimlow support.Hardware 7 25 September 2008 17:29
A500 logic analyzer tests Toni Wilen Coders. General 2 30 June 2008 17:52

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off

Forum Jump


All times are GMT +2. The time now is 21:02.


Powered by vBulletin® Version 3.8.11
Copyright ©2000 - 2021, vBulletin Solutions Inc.
Page generated in 0.08768 seconds with 16 queries