Apollo Team has new Cyclone 5 FPGA accellerator cards

[Mrs Beanbag]

tell you what i'd really like, if you could update the FPGA core from the Amiga side of things, if you could reconfigure the rest of the FPGA outside of the CPU core and use it for your own purposes. For a while i have imagined something like this as the natural evolution of the Blitter, because the core of the Blitter is a programmable LUT.

[meynaf]

Originally Posted by JimDrew

The FPGA Arcade Replay's CPU core offers full 68EC020 and 68020 modes. All 020 instructions are supported.

Shhhhhht ! Where will Gunnar's excuses for not implementing all instructions go if someone else shows it's indeed doable ?

[Gunnar]

Originally Posted by meynaf

Shhhhhht ! Where will Gunnar's excuses for not implementing all instructions go if someone else shows it's indeed doable ?

haha LOL,

There are of couse good technivcal reasons for doing and also for not doing it.

But lets first verify this claim, shall we?
Post like this were posted before by people based in simple misunderstandings.

[jbenam]

Originally Posted by meynaf

Shhhhhht ! Where will Gunnar's excuses for not implementing all instructions go if someone else shows it's indeed doable ?

Yaqube was the one who did the full 68020 core, right?

[JimDrew]

Originally Posted by Gunnar

Can you please tell us which core this is?
The TG68 is only partially compatible, it used to miss 68010 and 68020 instructions.

This is Mike's CPU core. I don't think there is a single piece of anything left in the FPGA Arcade's Amiga core that is based around the minimig stuff anymore. Mike had to re-write each of the custom chips from scratch to make them 100% identical to the real hardware. In the process there is now Lisa, Gayle, and other chips and things that have never existed. There are still some things work out, but most all AGA demos that beat on the hardware work perfctly, the IDE drive is emulated exactly, etc. 020 instructions all work as well. It's basically a complete A1200 emulation.

I am the North American distributor for the FPGA Arcade Replay. I got involved with the project because I wanted to get the Paula emulation correct (since I know Paula inside and out) so that it would run MY Amiga applications that beat on the hardware directly. WinUAE does not work with most anything I wrote because of some tricks I did (which work on ALL Amiga models). I am not a super FPGA guy (still learning), but I am able to look at VHDL code and know enough about it to make changes. The Amiga core is close to completion. There are already numerous other cores that are done and working (VIC-20, Atari 800, Collecovision, multiple stand-up arcade machines, etc.). It's a great product with a big FPGA.

[Gunnar]

Originally Posted by JimDrew

This is Mike's CPU core. I don't think there is a single piece of anything left in the FPGA Arcade's Amiga core that is based around the minimig stuff anymore.

I see.
The Sysinfo numbers you once provided were from this core?

Originally Posted by JimDrew

I am the North American distributor for the FPGA Arcade Replay.

Sounds interesting. When will people be able to buy it?


Cheers
Gunnar

[pandy71]

Originally Posted by JimDrew

Mike had to re-write each of the custom chips from scratch to make them 100% identical to the real hardware.

Hardware proven?

Originally Posted by JimDrew

I got involved with the project because I wanted to get the Paula emulation correct (since I know Paula inside and out) so that it would run MY Amiga applications that beat on the hardware directly. WinUAE does not work with most anything I wrote because of some tricks I did (which work on ALL Amiga models).

So... perhaps You can share details about internal Paula architecture?
There is some limited amount of information about DPLL (USPTO 4,780,844) and overall Paula architecture (USPTO 4,829,473) - but probably there is lot more than this.

[FrenchShark]

Originally Posted by pandy71

Hardware proven?



So... perhaps You can share details about internal Paula architecture?
There is some limited amount of information about DPLL (USPTO 4,780,844) and overall Paula architecture (USPTO 4,829,473) - but probably there is lot more than this.

This is really no big deal.
I have done it myself. I am sure Mike had no problem implementing that part.
Here is the DPLL verilog code :-)
Read has been tested. Write, not yet.

// This module is based on :
//
// Patent #4,780,844 from Commodore-Amiga Inc.
// DATA INPUT CIRCUIT WITH DIGITAL PHASE LOCKED LOOP

module mfm_dpll
(
input rst, // Global reset
input clk, // Ref. 21, 85 MHz clock
input clk_ena, // Ref. 21, 100 for HD, 100000 for DD, 100000000000 for SD
input dsk_rd_n, // Ref. 11, disk read port
output [15:0] buf_rd, // Ref. 15, read shift register
output buf_rdy, // Data buffer ready
input start, // DMA start strobe
input dma_on, // DMA active flag
input wr_mode, // Ref. 23, read (0), write (1)
input sync_arm, // MFM synchronization armed
input sync_ena, // MFM synchronization enabled
input [15:0] sync_word, // MFM synchronization word value
output sync_det // MFM synchronization detected
);

// ================================
// == Falling edge detector (71) ==
// ================================

reg [2:0] r_dsk_rd_cc; // Ref. 71
wire w_dsk_rd_edge; // Ref. 93

always@(posedge rst or posedge clk) begin
if (rst)
r_dsk_rd_cc <= 3'b111;
else if (clk_ena) begin
if (sync_arm | ~wr_mode)
r_dsk_rd_cc <= { r_dsk_rd_cc[1:0], dsk_rd_n };
end
end
assign w_dsk_rd_edge = r_dsk_rd_cc[2] & ~r_dsk_rd_cc[1];

// ================================
// == MFM/GCR bit flip-flop (81) ==
// == 16-bit shift register (15) ==
// ================================

reg r_bit_ff; // Ref. 81
reg [15:0] r_buf_rd; // Ref. 15

always@(posedge rst or posedge clk) begin
if (rst) begin
r_bit_ff <= 1'b0;
r_buf_rd <= 16'h0000;
end else if (clk_ena) begin
if (w_dsk_rd_edge)
r_bit_ff <= 1'b1;
else if (w_roll_over)
r_bit_ff <= 1'b0;
if (w_roll_over)
r_buf_rd <= { r_buf_rd[14:0], r_bit_ff };
end
end
assign buf_rd = r_buf_rd;

// ==============================
// == MFM synchronization word ==
// == MFM word alignment ==
// ==============================

reg r_sync_equ;
reg r_sync_det;
reg [3:0] r_bit_ctr;
reg r_buf_rdy;

always@(posedge rst or posedge clk) begin
if (rst) begin
r_sync_equ <= 1'b0;
r_sync_det <= 1'b0;
r_bit_ctr <= 4'd0;
r_buf_rdy <= 1'b0;
end else if (clk_ena) begin
// MFM synchronization
r_sync_equ <= ({ r_buf_rd[14:0], r_bit_ff } == sync_word) ? 1'b1 : 1'b0;
if (w_roll_over) r_sync_det <= r_sync_equ;
// MFM word alignment
if ((w_roll_over & r_sync_equ & sync_ena) | start)
r_bit_ctr <= 4'd0;
else if (w_roll_over)
r_bit_ctr <= r_bit_ctr + 4'd1;
if (((&r_bit_ctr & ~sync_arm) | (r_sync_equ & sync_ena)) & w_roll_over)
r_buf_rdy <= r_buf_rdy ^ dma_on;
end
end
assign sync_det = r_sync_det;
assign buf_rdy = r_buf_rdy;

// ==================================
// == Window history register (91) ==
// ==================================

reg [1:0] r_msb_hist; // Ref. 91

always@(posedge rst or posedge clk) begin
if (rst)
r_msb_hist <= 2'b00;
else if (w_dsk_rd_edge & clk_ena)
r_msb_hist <= { r_msb_hist[0], r_ph_adder[11] };
end

// ================================
// == 8-bit up/down counter (25) ==
// ================================

`define CTR_MAX_VAL 8'd159
`define CTR_AVG_VAL 8'd146
`define CTR_MIN_VAL 8'd133

reg [7:0] r_up_dn_ctr; // Ref. 25

always@(posedge rst or posedge clk) begin
if (rst)
r_up_dn_ctr <= `CTR_AVG_VAL;
else if (clk_ena) begin
if (start)
r_up_dn_ctr <= `CTR_AVG_VAL;
else if ((r_cnt_up) && (r_up_dn_ctr != `CTR_MAX_VAL))
r_up_dn_ctr <= r_up_dn_ctr + 8'd1;
else if ((r_cnt_dn) && (r_up_dn_ctr != `CTR_MIN_VAL))
r_up_dn_ctr <= r_up_dn_ctr - 8'd1;
end
end

// ==================================
// == Added value multiplexer (41) ==
// ==================================

`define ADD_LO_VAL 9'd34
`define ADD_HI_VAL 9'd258

wire [8:0] w_ctr_val;
wire [8:0] w_add_val; // Ref. 41

assign w_ctr_val = (r_add_four)
? ({1'b0, r_up_dn_ctr} + 9'd4) // Write mode add four
: {1'b0, r_up_dn_ctr}; // Normal mode

assign w_add_val = ({9{r_sel_low}} & `ADD_LO_VAL) // Negative phase correction
| ({9{r_sel_ctr}} & w_ctr_val) // No phase correction
| ({9{r_sel_high}} & `ADD_HI_VAL); // Positive phase correction

// =============================
// == 12-bit phase adder (43) ==
// =============================

reg [11:0] r_ph_adder; // Ref. 43

always@(posedge rst or posedge clk) begin
if (rst)
r_ph_adder <= 12'd0;
else if (clk_ena) begin
if (start)
r_ph_adder <= 12'd0;
else
r_ph_adder <= r_ph_adder + { 3'b000, w_add_val };
end
end

// ==========================
// == Adder roll-over (79) ==
// ==========================

reg r_msb_dly; // Ref. 79
wire w_roll_over; // Ref. 83

always@(posedge rst or posedge clk) begin
if (rst)
r_msb_dly <= 1'b0;
else if (clk_ena)
// Set when 111, cleared otherwise
r_msb_dly <= &r_ph_adder[11:9];
end
// 111 -> 000 : roll-over detection
assign w_roll_over = r_msb_dly & ~(&r_ph_adder[11:9]);

// ===============================
// == Add four instruction (89) ==
// ===============================

reg r_add_four; // Ref. 89

always@(posedge rst or posedge clk) begin
if (rst)
r_add_four <= 1'b0;
else if (clk_ena)
// Add 4 every 14 cycles during write mode
r_add_four <= (&r_ph_adder[10:8]) & wr_mode & ~sync_arm;
end

// ==============================
// == Freq. error decoder (73) ==
// ==============================

reg [3:0] r_freq_err; // Ref. 99
reg r_cnt_up; // Ref. 27
reg r_cnt_dn; // Ref. 29

always@(posedge rst or posedge clk) begin
if (rst) begin
r_freq_err <= 4'd0;
r_cnt_up <= 1'b0;
r_cnt_dn <= 1'b0;
end else if (clk_ena) begin
if (w_dsk_rd_edge) begin
// Compute frequency correction based on:
// - phase history
// - current phase
case ({r_msb_hist, r_ph_adder[11:9]})
5'b00000 : r_freq_err <= 4'b0100; // +4
5'b00001 : r_freq_err <= 4'b0011; // +3
5'b00010 : r_freq_err <= 4'b0010; // +2
5'b00011 : r_freq_err <= 4'b0001; // +1
5'b00100 : r_freq_err <= 4'b1000; // +0
5'b00101 : r_freq_err <= 4'b1001; // -1
5'b00110 : r_freq_err <= 4'b1010; // -2
5'b00111 : r_freq_err <= 4'b1011; // -3
5'b01000 : r_freq_err <= 4'b0000; // +0
5'b01001 : r_freq_err <= 4'b0000; // +0
5'b01010 : r_freq_err <= 4'b0000; // +0
5'b01011 : r_freq_err <= 4'b0000; // +0
5'b01100 : r_freq_err <= 4'b1000; // +0
5'b01101 : r_freq_err <= 4'b1001; // -1
5'b01110 : r_freq_err <= 4'b1010; // -2
5'b01111 : r_freq_err <= 4'b1011; // -3
5'b10000 : r_freq_err <= 4'b0011; // +3
5'b10001 : r_freq_err <= 4'b0010; // +2
5'b10010 : r_freq_err <= 4'b0001; // +1
5'b10011 : r_freq_err <= 4'b0000; // +0
5'b10100 : r_freq_err <= 4'b1000; // +0
5'b10101 : r_freq_err <= 4'b1000; // +0
5'b10110 : r_freq_err <= 4'b1000; // +0
5'b10111 : r_freq_err <= 4'b1000; // +0
5'b11000 : r_freq_err <= 4'b0011; // +3
5'b11001 : r_freq_err <= 4'b0010; // +2
5'b11010 : r_freq_err <= 4'b0001; // +1
5'b11011 : r_freq_err <= 4'b0000; // +0
5'b11100 : r_freq_err <= 4'b1001; // -1
5'b11101 : r_freq_err <= 4'b1010; // -2
5'b11110 : r_freq_err <= 4'b1011; // -3
5'b11111 : r_freq_err <= 4'b1100; // -4
default : ;
endcase
// No frequency correction
r_cnt_up <= 1'b0;
r_cnt_dn <= 1'b0;
end else begin
if (r_freq_err[2:0] != 3'd0) begin
// Apply frequency correction
r_freq_err[2:0] <= r_freq_err[2:0] - 3'd1;
if (r_freq_err[3]) begin
// Decrement frequency
r_cnt_up <= 1'b0;
r_cnt_dn <= 1'b1;
end else begin
// Increment frequency
r_cnt_up <= 1'b1;
r_cnt_dn <= 1'b0;
end
end else begin
// No frequency correction
r_cnt_up <= 1'b0;
r_cnt_dn <= 1'b0;
end
end
end
end

// ==============================
// == Phase error decoder (75) ==
// ==============================

reg [3:0] r_ph_err; // Ref. 101
reg r_sel_low; // Ref. 45
reg r_sel_ctr; // Ref. 47
reg r_sel_high; // Ref. 49

always@(posedge rst or posedge clk) begin
if (rst) begin
r_ph_err <= 4'd0;
r_sel_low <= 1'b0;
r_sel_ctr <= 1'b1;
r_sel_high <= 1'b0;
end else if (clk_ena) begin
if (w_dsk_rd_edge) begin
// Measure phase error
r_ph_err[3] <= r_ph_adder[11];
if (r_ph_adder[11]) begin
// Negative error
r_sel_low <= 1'b1;
r_sel_ctr <= 1'b0;
r_sel_high <= 1'b0;
r_ph_err[2:0] <= r_ph_adder[10:8];
end else begin
// Positive error
r_sel_low <= 1'b0;
r_sel_ctr <= 1'b0;
r_sel_high <= 1'b1;
r_ph_err[2:0] <= ~r_ph_adder[10:8];
end
end else begin
if (r_ph_err[2:0] != 3'd0) begin
// Apply phase correction
r_ph_err[2:0] <= r_ph_err[2:0] - 3'd1;
if (r_ph_err[3]) begin
// Negative phase correction
r_sel_low <= 1'b1;
r_sel_ctr <= 1'b0;
r_sel_high <= 1'b0;
end else begin
// Positive phase correction
r_sel_low <= 1'b0;
r_sel_ctr <= 1'b0;
r_sel_high <= 1'b1;
end
end else begin
// No phase correction
r_sel_low <= 1'b0;
r_sel_ctr <= 1'b1;
r_sel_high <= 1'b0;
end
end
end
end

endmodule

Enjoy !!

Frederic

[HardStep]

Originally Posted by Gunnar

1) We could sell the card as pure CPU upgrade earlier.

I recently started thinking about getting a 040 card to be converted into 060 or another 060 card to overclock and use with Mediator in a tower but pure FPGA CPU upgrade would be ****** awesome. Hope there are more people who are interested in just a fast CPU+ram option. Especially now when we have Indivision and soon ScanJuggler scandoublers, AGA-only machines with superfast CPUs would be a lot of fun too.

Would buy both of them, just CPU and full card, for sure. Sign me up

[JimDrew]

Originally Posted by Gunnar

I see.
The Sysinfo numbers you once provided were from this core?

Yes, debug core with no cache enabled. This is why I chatted with you. I wanted to find out just how fast your CPU core was compared to the full CPU core that Mike has.

Originally Posted by Gunnar

Sounds interesting. When will people be able to buy it?

Pretty soon. Mike just got done with the new FILEIO to allow high speed data transfers. We need that for raw flux images for the disk emulation (real flux data provided to Paula) as well as the hard drive. Some fixing of Alice is in the works last I was told.

[JimDrew]

Originally Posted by pandy71

Hardware proven?



So... perhaps You can share details about internal Paula architecture?
There is some limited amount of information about DPLL (USPTO 4,780,844) and overall Paula architecture (USPTO 4,829,473) - but probably there is lot more than this.

Yes, Mike is a bit nutty when it comes to direct comparisons to the hardware, shaving chips, x-raying dies, etc.

There are a LOT of details that I discovered about Paula that are well beyond the patent descriptions, and the code above will not emulate Paula fully. You are missing several key elements, and will be missing more when you add the writing support. The DMA integration is one of the biggest problems, and there is of course the GCR module that everyone misses.

[turrican3]

could it be possible technically to include aga to make amiga 500 compatible aga, and what's the limits of this approach ???
which could be the more crazy card for amiga 500 which could be done ?
Your card is already crazy !!! But where is the limit.
And an A4000 or a1200 could have better card ???
Would you like to make a completly new amiga ???
Like the natami team tried to do ???
Last one : is it possible to make ppc card in this way ??? And could it be a good idea.
When i saw your price for the card, i think there space for a more powerfull one, if there is no hardware limitation.
But be sure i'm already more than impressed with this one !

[FrenchShark]

Originally Posted by JimDrew

Yes, Mike is a bit nutty when it comes to direct comparisons to the hardware, shaving chips, x-raying dies, etc.

There are a LOT of details that I discovered about Paula that are well beyond the patent descriptions, and the code above will not emulate Paula fully. You are missing several key elements, and will be missing more when you add the writing support. The DMA integration is one of the biggest problems, and there is of course the GCR module that everyone misses.

Right, the PRECOMP is tricky in the write support.
GCR is not really used (maybe on some write protected games ? and if you want to read C64 disks ?).
For the DMA, I have a 3-word FIFO and the famous DMAL one-wire protocol between Paula and Agnus.
There is also the early read cycle for DMA Disk write and Blitter destination.
I guess you were refferring to that part ? The Minimig totally missed this point with its one-clock DMA cycle.

Regards,

Frederic

[FrenchShark]

Originally Posted by turrican3

could it be possible technically to include aga to make amiga 500 compatible aga, and what's the limits of this approach ???
which could be the more crazy card for amiga 500 which could be done ?
Your card is already crazy !!! But where is the limit.
And an A4000 or a1200 could have better card ???
Would you like to make a completly new amiga ???
Like the natami team tried to do ???
Last one : is it possible to make ppc card in this way ??? And could it be a good idea.
When i saw your price for the card, i think there space for a more powerfull one, if there is no hardware limitation.
But be sure i'm already more than impressed with this one !

The difficulty with AGA on A500/A2000 are the 8520s that must run at 1.4 MHz. You need at least a small FPGA card to replace the original 8520s (maybe there are 2MHz 8520s in DIL package somewhere ?).

Regards,

Frederic

[OlafSch]

Originally Posted by JimDrew

Yes, debug core with no cache enabled. This is why I chatted with you. I wanted to find out just how fast your CPU core was compared to the full CPU core that Mike has.




Pretty soon. Mike just got done with the new FILEIO to allow high speed data transfers. We need that for raw flux images for the disk emulation (real flux data provided to Paula) as well as the hard drive. Some fixing of Alice is in the works last I was told.

Pretty soon? What does that mean? When it is done in just 2 more weeks?

[JimDrew]

Originally Posted by FrenchShark

Right, the PRECOMP is tricky in the write support.
GCR is not really used (maybe on some write protected games ? and if you want to read C64 disks ?).
For the DMA, I have a 3-word FIFO and the famous DMAL one-wire protocol between Paula and Agnus.
There is also the early read cycle for DMA Disk write and Blitter destination.
I guess you were refferring to that part ? The Minimig totally missed this point with its one-clock DMA cycle.

Regards,

Frederic

You are missing part of the data seperator, specifically for handling timings outside of the normal 2us/4us bitcell size. That code does not handle weakbit or strongbit protections correctly. You need GCR for handling Mac formatted disks, loading some copy protected Amiga disks, and also for analyzing copy protected MFM disks (this is a neat way to scan a MFM disk and see patterns). You must be able to turn on/off/on the DMA randomly, and also change the DMA length counter on the fly without affecting the incoming data. There are a few other little things as well. Paula is far more complicated than most people realize, and it took me a long time to be able to understand how the disk portion really works and come up with the tricks that I did with my copy and converter programs. I learned quite a bit when I changed the speed of Paula via SYBIL.

[JimDrew]

Originally Posted by OlafSch

Pretty soon? What does that mean? When it is done in just 2 more weeks?

Mike has had piles of boards for a year, all waiting for the Amiga core to be finalized. Mike has sold numerous boards to FPGA developers, so that is where a lot of the cores that already exist for the board have come from.

Mike and Wolfgang made the FPGA Arcade Replay board a development platform. It makes it easy to take an existing FPGA project and move it to the Replay because there are several hardware abstraction layers available - such as a video system (with variable clocking, DVI, SVideo/Composite outputs), a high-def stereo audio DAC, memory system, on screen display system with menuing, PS/2 mouse and keyboard support, high speed file I/O with a SD media card, etc. All of these modules are imbedded in the loader that pops up when you switch on the Replay. Your core just needs to take advantage of these modules (or replace them if you want - info about the board including complete schematics is readily available).

I expect to be demoing the completed Amiga core at CommVex at the end of the month.

[Lord Aga]

Originally Posted by JimDrew

Mike has had piles of boards for a year, all waiting for the Amiga core to be finalized.

But... why ? It isn't an Amiga-only board. We could have been having fun with simpler Speccy or C64 cores all this time.

[pandy71]

Originally Posted by FrenchShark

This is really no big deal.
I have done it myself. I am sure Mike had no problem implementing that part.
Here is the DPLL verilog code :-)
Read has been tested. Write, not yet.
.
.
.
.
Enjoy !!

Frederic

Thanks FrenchShark for nice surprise!!! But side to DPLL there is more things in Paula where there is no information at all (similar for example for Blitter patent where line mode is totally ignored - perhaps due patents violation? Maybe same situation in Paula case - mentioned by Jim GCR functionality - also not covered by HRM)

Originally Posted by JimDrew

Yes, Mike is a bit nutty when it comes to direct comparisons to the hardware, shaving chips, x-raying dies, etc.

There are a LOT of details that I discovered about Paula that are well beyond the patent descriptions, and the code above will not emulate Paula fully. You are missing several key elements, and will be missing more when you add the writing support. The DMA integration is one of the biggest problems, and there is of course the GCR module that everyone misses.

Originally Posted by JimDrew

You are missing part of the data seperator, specifically for handling timings outside of the normal 2us/4us bitcell size. That code does not handle weakbit or strongbit protections correctly. You need GCR for handling Mac formatted disks, loading some copy protected Amiga disks, and also for analyzing copy protected MFM disks (this is a neat way to scan a MFM disk and see patterns). You must be able to turn on/off/on the DMA randomly, and also change the DMA length counter on the fly without affecting the incoming data. There are a few other little things as well. Paula is far more complicated than most people realize, and it took me a long time to be able to understand how the disk portion really works and come up with the tricks that I did with my copy and converter programs. I learned quite a bit when I changed the speed of Paula via SYBIL.

so any chance to share such details in separate topic for example http://eab.abime.net/showthread.php?t=19676 ?

Also SYBIL sounds curious - i've read about SYBIL few times but in Europe not many people use this HW - do SYBIL is reprogrammable (controlled by software) clock source connected to video port (and by this able to change system speed in variable way)?

Thanks in advance!

Originally Posted by turrican3

could it be possible technically to include aga to make amiga 500 compatible aga, and what's the limits of this approach ???

AFAIR Commodore mentioned such possibility in Budgie description - Budgie should be able perform conversion between 16 bit CPU bus and 32 bit CHIP AGA bus.
So this should be possible - A3000 schematics have something like Budgie but on TTL - bunch of 74646 buffers mostly.

Originally Posted by FrenchShark

The difficulty with AGA on A500/A2000 are the 8520s that must run at 1.4 MHz. You need at least a small FPGA card to replace the original 8520s (maybe there are 2MHz 8520s in DIL package somewhere ?).

Regards,

Frederic

Are You sure? E clock is same for A1000 and for A4000 - seem that 8520 are the same speed...

[FrenchShark]

Originally Posted by JimDrew

You are missing part of the data seperator, specifically for handling timings outside of the normal 2us/4us bitcell size. That code does not handle weakbit or strongbit protections correctly. You need GCR for handling Mac formatted disks, loading some copy protected Amiga disks, and also for analyzing copy protected MFM disks (this is a neat way to scan a MFM disk and see patterns). You must be able to turn on/off/on the DMA randomly, and also change the DMA length counter on the fly without affecting the incoming data. There are a few other little things as well. Paula is far more complicated than most people realize, and it took me a long time to be able to understand how the disk portion really works and come up with the tricks that I did with my copy and converter programs. I learned quite a bit when I changed the speed of Paula via SYBIL.

IIRC, the DPLL code I posted handles timings outside 2us/4us cell size as long as the counter is within CTR_MIN_VAL and CTR_MAX_VAL.
GCR (4us bit cell) is handled with the clock enable, I even added HD floppy mode with a faster clock enable. I guess you have added the HD mode on the FPGA Arcade too (maybe even variable bit cell mode) ?

Regards,

Frederic