14Mhz Accelerator

[Methanoid]

I have nothing but respect for the talents you designers are showing.. wish we had this back in the day too....

More memory than 1Mb though maybe?

[Mathesar]

Originally Posted by Methanoid

More memory than 1Mb though maybe?

Maybe, yes. One of the nice things about this (and the original design) is the simplicity of the design. Adding 1Mb @$C00000 was easy as I only needed 3 extra logic IC's. There is room at that address range for up to 1,75Mb though.
So a future version could have more memory.
For even more memory we would have to move to Zorro II space but that requires a lot more logic.


This accelerator should be seen as a "moderate" accelerator. Just enough to play the upcoming dread at a higher framerate or prevent any slowdowns when you "nuke" 100 Lemmings.

[utri007]

this looks nice and simple. If it works, I would like to get one, if possible.

[Mathesar]

Originally Posted by utri007

this looks nice and simple. If it works, I would like to get one, if possible.

If it works I will post all design files here for everyone to build.

[Sim085]

Is there a version of this which just gives the 14Mhz increase with no fastRAM and no IDE?

I know some will say it does not make sense, however there are expansions that already provide just fastRAM and IDE. With this they could possible now have a 14MHz improvement.

[Mathesar]

The board I designed could also be build without the fast ram. It's just a matter of leaving some components out and making 2 jumpers.

But you know what I'm going to say..
Without fast ram that also runs at 14MHz the speed gain would be very, very minimal.
If you already have a fast ram / ide expansion and you stack this card on top of it than the fast ram will still run at 7MHz hence there will no be speed improvement.

[utri007]

Originally Posted by Mathesar

The board I designed could also be build without the fast ram. It's just a matter of leaving some components out and making 2 jumpers.

But you know what I'm going to say..
Without fast ram that also runs at 14MHz the speed gain would be very, very minimal.
If you already have a fast ram / ide expansion and you stack this card on top of it than the fast ram will still run at 7MHz hence there will no be speed improvement.

Having this board without a fast ram is quite much pointless. Just wondering, Supra turbo had a tiny 16kb data cache wich make a huge difference for a performance with external zorro II fast ram. Would 1mb ram make same effect if I have a lets say 4mb zorro II ram? http://amiga.resource.cx/exp/supra28

I woun't be able to build this myself.

[Sim085]

Originally Posted by Mathesar

...and you stack this card on top of it than...

... what if you stack it below it?
Like a re-locator board with steroids (and obviously the CPU socket would be just in the same form factor as the original).

[Mathesar]

Originally Posted by Sim085

... what if you stack it below it?
Like a re-locator board with steroids (and obviously the CPU socket would be just in the same form factor as the original).

If the logic on the ram board would keep up then, yes, that could work.

[Mathesar]

Originally Posted by utri007

Having this board without a fast ram is quite much pointless. Just wondering, Supra turbo had a tiny 16kb data cache wich make a huge difference for a performance with external zorro III fast ram. Would 1mb ram make same effect if I have a lets say 4mb zorro II ram? http://amiga.resource.cx/exp/supra28

I woun't be able to build this myself.

The problem is that the 1MB is not a cache. It would be classified by the OS as slow ram and given a lower priority than any zorro II/III fast ram. It would thus never be used until your 4MB is full.
Having a real cache is possible but needs more logic. And that would mean GAL's or CPLD's and that takes away the charm of this little accelerator.

[AJCopland]

Originally Posted by Mathesar

If it works I will post all design files here for everyone to build.

Yay! That's awesome of you!

[Jope]

Originally Posted by Mathesar

The problem is that the 1MB is not a cache. It would be classified by the OS as slow ram and given a lower priority than any zorro II/III fast ram. It would thus never be used until your 4MB is full.
Having a real cache is possible but needs more logic. And that would mean GAL's or CPLD's and that takes away the charm of this little accelerator.

For 1.3 lovers this is not a problem, as C00000 RAM has higher priority than Z2 RAM. :-) Just remove FastMemFirst from your startup-sequence.

[keithamiga1200]

Awesome

Originally Posted by Mathesar

I like this accelerator a lot. The fact that it uses no programmable logic but just 7400 logic makes it easy to build for everyone.
As the current implementation has some issues I went back Livio's and Jorg's original design. I have drawn out all the waveforms of that design on a piece of paper and to me everything seems sound. The AS/DTACK timing is perfect and the E-clock is almost perfect. So, I think the original design *should* work. However, lacking any fastram the design barely accelerates, just a few percent.
So, I simplified the original design a bit (eliminated the hex inverter), removed the on/off switch, changed the clock doubler and added 1Mbyte of zero waitstate ranger ram. Still using only 7400 logic.
The result is an accelerator with 1MByte of fastram that should be about 2.5 times faster than an A500. I just ordered the boards+parts.
Fingers crossed that it works!
Attachment 71332

[Snigelson]

Originally Posted by Mathesar

I like this accelerator a lot. The fact that it uses no programmable logic but just 7400 logic makes it easy to build for everyone.
As the current implementation has some issues I went back Livio's and Jorg's original design. I have drawn out all the waveforms of that design on a piece of paper and to me everything seems sound. The AS/DTACK timing is perfect and the E-clock is almost perfect. So, I think the original design *should* work. However, lacking any fastram the design barely accelerates, just a few percent.
So, I simplified the original design a bit (eliminated the hex inverter), removed the on/off switch, changed the clock doubler and added 1Mbyte of zero waitstate ranger ram. Still using only 7400 logic.
The result is an accelerator with 1MByte of fastram that should be about 2.5 times faster than an A500. I just ordered the boards+parts.
Fingers crossed that it works!
Attachment 71332

God I should have read through this thread earlier. A few months ago I was thinking "hmm, I need a new project". So I made an IDE and 2 MB FastRam board. That worked out well.

So then I needed a relocator to fit it better in my 500. And why not add a clock doubler on that relocator.

That didn't go as well, since I followed the schematics by the first poster. I thought there were a few strange things, and I did compare with the schematics by Livio Plos, but I thought nah, I'm just imaging.

If yours work, I'd be very grateful if you could share your schematics.

Crappy picture attached. If anyone is wondering, they are both 4 layer boards. I could probably have done the relocator on 2 layers. The RAM board probably not at that size. Also I like signal integrity

[Mathesar]

Originally Posted by Snigelson

God I should have read through this thread earlier. A few months ago I was thinking "hmm, I need a new project". So I made an IDE and 2 MB FastRam board. That worked out well.

So then I needed a relocator to fit it better in my 500. And why not add a clock doubler on that relocator.

That didn't go as well, since I followed the schematics by the first poster. I thought there were a few strange things, and I did compare with the schematics by Livio Plos, but I thought nah, I'm just imaging.

If yours work, I'd be very grateful if you could share your schematics.

Crappy picture attached. If anyone is wondering, they are both 4 layer boards. I could probably have done the relocator on 2 layers. The RAM board probably not at that size. Also I like signal integrity

Nice RAM/IDE board! What design(s) is it based on? Or is it your own? There is not a lot of logic on that board... I needed 3 7400 IC's just to do the RAM part. Although in my case I can't use the normal Amiga DTACK termination (RAM overlaps with ranger area and I need to run the RAM at 14MHz) complicating matters somewhat. I agree about the 4 layers. However, I wanted to keep things cheap . I did pay a lot of attention to the decoupling and the ground path though.

And yes, I will share the design as soon as I've confirmed it works!

[Snigelson]

Originally Posted by Mathesar

What design(s) is it based on? Or is it your own? There is not a lot of logic on that board...

The RAM part is based on this design: https://blog.sector101.co.uk/2019/07...ram-expansion/. Basically just a 74HC138 as an address decoder (plus a single inverter), it just puts the 2 MB at $200000-$3FFFFF.

I'm somewhat experienced at drawing PCBs, much less experienced with Amiga and 68k stuff. So I don't know if there could be any issues not using the bus arbitration signals in this design. It's faster (1.37 times A600 according to SysInfo) and I haven't noticed anything glitchy yet. I'm hoping I can pop it onto the 14 MHz board and it will just work

[Mathesar]

Originally Posted by Snigelson

The RAM part is based on this design: https://blog.sector101.co.uk/2019/07...ram-expansion/. Basically just a 74HC138 as an address decoder (plus a single inverter), it just puts the 2 MB at $200000-$3FFFFF.

I'm somewhat experienced at drawing PCBs, much less experienced with Amiga and 68k stuff. So I don't know if there could be any issues not using the bus arbitration signals in this design. It's faster (1.37 times A600 according to SysInfo) and I haven't noticed anything glitchy yet. I'm hoping I can pop it onto the 14 MHz board and it will just work

The design as you built it works fine as you use it now and probably also when you put a clock doubler in front of it. However, the 14MHz can't really benefit from it as the DTACK is still generated by Gary at a "7MHz pace". You thus won't see any acceleration by the faster CPU. In my design I hide any accesses to the RAM from the Amiga by blocking the address strobe (AS) and generating a faster DTACK. This allows the RAM to be accessed at the full CPU speed.

[Mathesar]

A little update with some good and some bad news.

The PCB's I ordered are in and they look good. They also fit quite nicely. There will be no need for a relocator board and the metal shield will fit just fine. I have begun with testing the clock doubler. This version has a 7->14MHz clock doubler based upon an old-skool 74HCT4046 PLL. So, there is no need for a patch wire to Gary to feed in the CDAC clock. This is a standalone plug&play board. But, anyone who ever designed PLL's knows they can be quite temperamentful . In this case the PLL wouldn't lock because of a fundamental mistake in the loop filter I designed (the loop bandwidth was way too small). So I corrected that and that got me a nice 53% duty cycle 14MHz signal right out of the box. However, the falling edge of the 14MHz clock was jittering. It turned out this was caused by the signal level of the Amiga's 7MHz clock that doesn't swing completely to 5V. Apparently this mis-biased the PLL's input amplifier causing jitter. By capacitively feeding the 7MHz clock into the 74HT4046 this was resolved. The clock is still a tiny bit jittery but not enough to cause any problems I think.

So, the bad news is that the PCB needs a patch to add the coupling capacitor and make it work. However, it is just a tiny patch and once the rest is working I will release fiixed gerbers, schematic, etc.

EDIT: Will post some scope screens if I have some time. Duty cycle is close to 50% and there is about 15.25ns delay between the 7MHz and the 14MHz signal. The delay is a tiny bit high but yeah, the HCT4046 is not terribly fast.. I'll see how it goes when the rest of the circuit is up and running.

EDIT2: scope screenshot:
.
Delay is less than estimated, just 18ns. I also made a final tweak to the loop filter and now the jtter is 2ns peak-peak. Duty cycle can be made 50% by tweaking a resistor value.

[Mathesar]

Quick update, i have assembled the board without the fast ram to test the cpu/clock doubler.
Unfortuntely it doesn't work properly yet. AS/DTACK and E/VPA/VMA timing looks great but somehow the boot process stops after the first drive click and I am left with a white screen. It looks like the cpu is then halted and only processes interrupts.
It does boot into chucky's diagrom though. Graphic/sound/keyboard all works fine. Memory test I don't understand fully (shadowram?) but what really goes wrong is cia test and drive tests. Cia's run too slow according to the test (especially the hsync one) and sometimes the system even crashes on that part. Now, at this point I am suspecting interrupt timing. Interrupts might be sampled too early by the 14mhz cpu and triggering the wrong interrupt levels. Does this make sense?

[hooverphonique]

How does the generated E-clock relate to the orignal 7MHz clock as compared to a standard amiga?