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Old 30 March 2018, 11:22   #21
Toni Wilen
WinUAE developer
Join Date: Aug 2001
Location: Hämeenlinna/Finland
Age: 43
Posts: 22,129

I think original reason was 68030 cache related bug/feature: long aligned writes always get cached if write allocate cache mode is enabled, even if write goes to hardware level (CI pin active) cache-inhibited memory. Only MMU level cache inhibit works properly in this situation.

CPU wrote something to chip ram, and because it was long and aligned write, it also got stored in data cache. Then blitter modified same memory. Finally CPU was used to read from address that was previously written to: data came from cache, not from memory that blitter modified.

EDIT: This happens very rarely because cache is so tiny.
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