Logic analyzer: Was Better (perhaps) A500 compatibility

[demoniac]

Excellent findings. To me this is one step closer to recreating the Amiga prototype with breadboards.

[Toni Wilen]

New logic analyzer findings (it has been too long..)

I finally decided to snoop RGA (custom register address bus) bus. Should have done this ages ago but I was stupid and too lazy

RGA = custom address accessed, WE = write enable, INT3 = Agnus int3 pin, DMAL = Paula DMAL pin (not used yet), IPL = CPU interrupt level.

Guess whats happening in these images? (hint in image names)

Apparently every custom chip number is directly available in RGA bus, even if it is Agnus internal register. (RGA is used to transfer data to/from Denise and Paula, for example Agnus bitplane DMA puts BPLxDAT to RGA and does DMA from chipram)

This means blitter line mode cycle diagram mystery will be finally solved in few days.

EDIT: delay between bltsize and first DMA transfer looks interesting and is quite long..

[sink]

toni u are a god! thk for your time, patience and devotion about "I think this explains problems with demos with vector objects because WinUAE's linedraw uses too many cycles depending on line type.. (testing soon)", you think that can be a solution for this probleme for exemple demos of virtual dream in the middle we can see that (the rest work like a charm):

[Toni Wilen]

Line draw mode was boring, didn't find anything interesting

It is -C-D-C-D-C-D except write is free cycle when in onedot mode and no pixel needs to be drawn. (nothing new here)

3 free cycles between write to BLTSIZE and first blit cycle are also free (this isn't exactly emulated yet) but this can't fix above demo either..

ADDED: I guess copper and blitter cycles don't align properly causing lost cycles (demo writes blitter registers using copper)

[sink]

oki thk for this info , like i'm a a500 maniak , please continue your work about the 500

[boing_1000]

Toni you work some mysterious magic

A logic analyzer, though...haha I admire your dedication.

[Toni Wilen]

Yes, necropost but on mostly on topic

Logic analyzer upgrade. After almost 14 years later.. DSLogic U3Pro32. Still to do: scope upgrade. Possibly Siglent SDS2104X Plus. (EDIT: scope upgrade done autumn 2021 + 16ch LA adapter)

Main reason was much larger internal RAM (enough space for dozens of frames), much more than Logicport which barely had enough memory for single scanline. (2k samples@32 channels vs 2G divided by number of channels without RLE compression)

Software is also much faster and supports programmable (in Python) decoders. Screen capture shows quickly made RGA to register names decoder. (No, I don't remember all register numbers!)

Data bus uses generic "Parallel" decoder which I only modified to support 16-bits (original only supports up to 8). "AmigaRGA" is also based on "Parallel".

Oddly enough software does not have built-in signal grouping support so you have to use existing decoders or write your own to get useful output.

[Exodous]

I've been looking for a logic probe recently and so I Googled the following - no quotes etc. just what is typed below:

DSLogic U32Pro32

Google comes back with no results at all. I can't ever remember seeing that!

Did you mean the U3Pro32?

[Toni Wilen]

Fixed

[Daedalus]

I use an earlier analyser from DSLogic, and it's great. I'm using the Sigrok software with it instead though, and it allows grouping of signals. It might be worth checking out Sigrok as an alternative. (Incidentally, the DSView software is based on Sigrok sources but with some changes to the UI.)

[Toni Wilen]

Originally Posted by Daedalus

I use an earlier analyser from DSLogic, and it's great. I'm using the Sigrok software with it instead though, and it allows grouping of signals. It might be worth checking out Sigrok as an alternative. (Incidentally, the DSView software is based on Sigrok sources but with some changes to the UI.)

U3Pro versions are not (yet?) supported by Sigrok software. But it does not really matter, custom decoder fixes the problem better than grouping

[zero]

Originally Posted by Toni Wilen

U3Pro versions are not (yet?) supported by Sigrok software. But it does not really matter, custom decoder fixes the problem better than grouping

I was considering the DSLogic too. I was looking at the basic model because it is supported by Sigrok. I like the look of the Kingst logic analysers too, but only the lower end models are supported.

One thing about the DSLogic, they don't mention what the analogue bandwidth is. It might be able to sample at 400MHz, but what is the highest frequency signal it can reliably capture? For debugging USB some of the lower end logic analysers are too slow. I guess that's not so much of an issue for you with Amiga stuff, at least for the stuff Commodore released.

My fantasy instrument would be a USB oscilloscope with 4 channels and 100MHz or more bandwidth, plus a 16 channel logic analyser. It seems like some of the Siglent scopes fit the bill, and Sigroks says that they are supported, but I can't actually find anyone who has used them and who can report on how well they actually work.

[Toni Wilen]

Originally Posted by zero

One thing about the DSLogic, they don't mention what the analogue bandwidth is. It might be able to sample at 400MHz, but what is the highest frequency signal it can reliably capture? For debugging USB some of the lower end logic analysers are too slow. I guess that's not so much of an issue for you with Amiga stuff, at least for the stuff Commodore released.

Yeah, ~100MHz is perfectly fine for my purposes.

My fantasy instrument would be a USB oscilloscope with 4 channels and 100MHz or more bandwidth, plus a 16 channel logic analyser. It seems like some of the Siglent scopes fit the bill, and Sigroks says that they are supported, but I can't actually find anyone who has used them and who can report on how well they actually work.

I have Siglent SDS2104X Plus + 16ch LA adapter. (bought last september). In my opinion (but I haven't used it for more than few days *) is quite annoying to use from scope interface compared to PC software (It does have touch screen and even VNC support = can control it from PC via network but it still is annoying compared to DSLogic)

*) Photo attached. DSLogic connected to RGA and data bus (and sync signals and few others) and Siglent connected to DRAM address bus. Currently trying to solve how bitplane + refresh/strobe conflict actually "works". It would have been simpler with 48ch+ LA but..

[TEG]

Originally Posted by Toni Wilen

As the diagram shows, only drawn pixels are written back (bus is free for other uses when no pixel drawn) I thought blitter always writes data back, even if there is no pixel drawn..

What do you mean by "the blitter writes data back". The blitter write data two times?

[Toni Wilen]

Originally Posted by TEG

What do you mean by "the blitter writes data back". The blitter write data two times?

I mean not all line draw D cycles necessarily write to chip ram.

Blitter line draw always does C reads but D write (you could also call it C write..) only happens when line pixel needs to be written. In onedot mode, if pixel does not need to be written, D write does not happen and bus cycle is free for other DMA channels.

[zero]

Originally Posted by Toni Wilen

I have Siglent SDS2104X Plus + 16ch LA adapter. (bought last september). In my opinion (but I haven't used it for more than few days *) is quite annoying to use from scope interface compared to PC software (It does have touch screen and even VNC support = can control it from PC via network but it still is annoying compared to DSLogic)

I think scope LAs are never going to be very good. I'd only get one if it was usable with Sigrok.

Have you tried the Siglent with Sigrok? It is supposed to be supported and in theory could be a really powerful tool, but I suspect that in practice it's limited by the scope's memory depth.

[gralco]

Originally Posted by zero

I think scope LAs are never going to be very good. I'd only get one if it was usable with Sigrok.

Have you tried the Siglent with Sigrok? It is supposed to be supported and in theory could be a really powerful tool, but I suspect that in practice it's limited by the scope's memory depth.

I added a pull request in Sigrok Pulseview to support the SDS2000X Plus series, feel free to test it and give feedback: https://github.com/sigrokproject/libsigrok/pull/176

[zero]

Originally Posted by gralco

I added a pull request in Sigrok Pulseview to support the SDS2000X Plus series, feel free to test it and give feedback: https://github.com/sigrokproject/libsigrok/pull/176

Thanks, that's encouraging.

If you have experience in this area it would be interesting to know how the scope's LA works, in terms of if you can capture say 10 seconds of data. There's really very little information, e.g. does it support compression. I get the impression it's mostly for correlation with an analogue signal, not deep LA use.

[gralco]

Originally Posted by zero

Thanks, that's encouraging.

If you have experience in this area it would be interesting to know how the scope's LA works, in terms of if you can capture say 10 seconds of data. There's really very little information, e.g. does it support compression. I get the impression it's mostly for correlation with an analogue signal, not deep LA use.

Unfortunately, I don't have LA probes for it (yet), so my patch is just for the analog side.

The instrument's digital channels have a max sample rate of 500MSa/s and a memory depth of 50Mpts/ch, so if you're trying to capture something that's 10 seconds long then you're only going to get 5MSa/s. That means for your 10s capture your signal is going to need to be 2.5MHz or slower.

[zero]

Originally Posted by gralco

Unfortunately, I don't have LA probes for it (yet), so my patch is just for the analog side.

The instrument's digital channels have a max sample rate of 500MSa/s and a memory depth of 50Mpts/ch, so if you're trying to capture something that's 10 seconds long then you're only going to get 5MSa/s. That means for your 10s capture your signal is going to need to be 2.5MHz or slower.

Yeah, it would be fine if they had compression but they don't seem to. Useless for the stuff I am working on like USB (12MHz). I find that even 2x the signal frequency is unreliable, e.g. I have a 24MHz USB LA but it can rarely decode USB packets and most USB peripherals use a 48MHz sample clock.