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Old 12 October 2016, 19:32   #221
Toni Wilen
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Quote:
Originally Posted by NorthWay View Post
Thx. (I'm (still/again) trying to do a Gauntlet style split for a right hand side info panel and I think the numbers add up for it being possible.)

When you increase bplcon1 scroll delay values during active display, what is shown in the "gap" that you create? Is it DFF180, last pixel stretch, pixels repeated, or something else?
(Yeah, I can't wait to get my 4000 back so I can test stuff like this...)
Zero bits. Check also http://eab.abime.net/showthread.php?t=71437

Quote:
Do the Amiga chips have any internal logic that behaves in a similar fashion to the Atari ST chips (see for example the talk here [ Show youtube player ]) so that they can be manipulated to do be "confused" and do things they weren't intended to?
(Basically using strict timing to force unintended internal states from my understanding.)
AFAIK only blitter can get confused. (by modifying BLTCON0 when blitter is active)

EDIT: and it is possible to force bitplane dma overrun, causing refresh cycle conflicts that messes up graphics.

Last edited by Toni Wilen; 12 October 2016 at 19:53.
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Old 28 October 2016, 15:39   #222
NorthWay
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On the topic of the hw logic; has anyone heard anything from the Visual6502 crew or anyone else working on de-capping the chips? Did Jens say he had done it?

Oh, and was there ever a summary list of registers that had to be updated every frame (i.e. best used in a copperlist) and which ones that would reuse last value written?

Bonus: 5.25" floppydrives - do they work differently from 3.5"? Can a gcr disk be read as an MFM image? Are there any alternative(/more effective) encodings to the official one that still adhere to the official MFM restrictions? I vaguely remember some old Psygnosis interview claiming 1.2M? 1.3M? 1.6M? format on a disk, but I don't know if they were breaking the rules. What makes 81/82 tracks (or more) work or not? Is there space for a full 11 sectors on 81+?
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Old 01 November 2016, 12:14   #223
Toni Wilen
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I don't think that is really undocumented enough for this thread.. (and floppy mechanism or size has nothing to do with encoding)
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Old 14 January 2017, 16:35   #224
Toni Wilen
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DMA mode sprite interesting side-effect if sprite's x-starting position is earlier than sprite's last or both DMA slots.

Sprite shift register is loaded immediately when x-coordinate matches and sprite is armed, DATA or DATB accesses or contents won't make any difference.

This means previous line's data is shown if new DATA or DATB has not been written. "Worst" case is when x matches between sprite's DMA slots, first sprite plane is correct, second plane has previous data. Final side-effect is last line appearing twice, first normally, then second time in next line.

Original report: http://eab.abime.net/showthread.php?t=85482
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Old 24 April 2017, 19:18   #225
Toni Wilen
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Blitter BDAT special case

Blitter B channel "B old" value (see HRM blitter diagram) is only cleared at blitter startup if channel is enabled.

Normally this does not cause any unexpected side-effects and is totally harmless. Except if previous blit's (with B channel enabled) last B channel read was non-zero, following blit has B channel disabled, B channel shift is non zero (for example B channel shift was used in previous blit) and BDAT is CPU (or copper) loaded with some static value. Because B channel shift is done instantly, shift count number of bits from "B old" will be shifted in, changing the data you loaded and it is not necessarily zeros that get shifted in. After BDAT load modifying shift value makes no difference.

This kind of situation is really rare but it has happened at lest once: http://eab.abime.net/showpost.php?p=...9&postcount=31

So always clear B-shift before manually setting BDAT, not after

ADAT works differently, "A old" seems to be always zeroed at startup.
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Old 24 April 2017, 21:06   #226
Toni Wilen
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Unaligned FMODE

FMODE>0 and address not aligned to fetch size:

FMODE=1 and FMODE=2

Load 32-bit value (from address AND ~3)
If address is not divisible by 4: lower 16-bit is copied to upper 16-bit.
If FMODE=2 and address is divisible by 4: upper 16-bit is copied to lower 16-bit

FMODE=3:

Load 64-bit value (from address AND ~7)
If address is not divisible by 8: lower 32-bit is copied to upper 32-bit
If address is not divisible by 4: do the same to both 32-bit halves: copy lower 16-bit to upper 16-bit.
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