memory access speed question

[TCD]

Think we got what you are on about already, but my question was why you go on OT when it's clear that Lord Riton isn't interested in what you suggested. With me now or do I have to remove any further Natami fanboism in this thread? Clear enough matthey?

[dissident]

Originally Posted by Kalms

Chipmem and fastmem accesses are different. To be precise, chipmem accesses are uncached. (so they behave largely the same way on all 68020+ systems.) Also, chipmem is very slow compared to the CPU clockrate.


If you read from a chipmem location, the CPU will stall during the entire duration of the memory read operation. This is because the CPU it needs the value stored in the memory location before the read operation can be completed.

If you write however, in most system configurations the write will get chucked into a buffer, and then the CPU continues processing other stuff while the bus interface is busy. (On most accelerator board there is such a write buffer on the accelerator board. In addition, the 68060 has a 4-slot write buffer internally in the CPU.) If any subsequent instruction tries to hit the bus while there are still pending writes, then the CPU will stall until the bus is available again.

For 50MHz accelerator boards, the bus will typically remain busy for 26-28 cycles after you have performed a chipmem write. During that period, don't touch the bus.

This is the best explanation I ever read about this topic, Kalms. I guess writing to CUSTOM chip addresses which are also uncached like the INTREQ register has the same effect.

[NorthWay]

(Nice necro, let me add to it: )
Strictly speaking, you could futz around with caching modes for chipram in your own program (not much support for such endeavors - more or less 040/060 needed).
The result would be that you need to flush the cache or addressing range before viewing it, and best case might be that you possibly get to fill any holes in your chipmem access, worst case you would get stalls if the cache writes out 4 longs each time a cache line is emptied.