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Old 19 May 2018, 20:05   #41
SpeedGeek
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** 10TH NEWS UPDATE **

v1.8 Released!
- Reworked the code to eliminate a serious (but seldom noticed) data transfer corruption bug for the case of multiple DMA drivers in the same system. Special Thanks to Ralph Babel for his excellent knowledge on this topic.

Last edited by SpeedGeek; 19 May 2018 at 20:18.
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Old 21 May 2018, 17:53   #42
SpeedGeek
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** 11TH NEWS UPDATE **

v1.9 Released!
- Fixed "D2 Register Not Preserved" coding bug in PreDMA.
Most DMA drivers don't seem to need it preserved but
Thanks to Cosmos for reporting it anyway. Moved PostDMA
Nest count code to user section of code. This eliminates
any calls to Supervisor when the count is more than 1.
v1.9BR Added new "Experimental" code which should allow only
DMA targeted 16MB blocks of Fast RAM to change to Write
Through mode. This "In Theory" allows the other 16MB
blocks to remain in Copyback mode. This can only benefit
"Big RAM" systems with 32MB+ of Fast RAM and ONLY when
these systems run apps which use the extra Fast RAM.
WARNING: Use at you own risk!

CACHEDMABENCH:
v1.0 - First release
v1.1 - Fixed address and size bugs in FC loop code which
could have affected the results.
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Old 23 May 2018, 21:18   #43
starship
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A4000 - cyberstorm mk3 72mhz - 128mb fastram

Without Fastcache040

CacheDMAbench 1.1 ©SpeedGeek 2018
---------------------------------
Public memory CacheDMA FCs: 9500
Chip memory CacheDMA FCs..: 500
Total CDMA Function Calls.: 10000
Elapsed time Microseconds.: 393637

With Fastcache040

CacheDMAbench 1.1 ©SpeedGeek 2018
---------------------------------
Public memory CacheDMA FCs: 9500
Chip memory CacheDMA FCs..: 500
Total CDMA Function Calls.: 10000
Elapsed time Microseconds.: 113858
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