Zorro III Bus Specifications wanted

[Shadowfire]

TNT, if you manage to get the 5V I/O interface up and running, could you please leave a message about what level shifters you are using? I'm prepping for something a bit more... complex than my last project, tentatively looking at the Cyclone EP3C16 (although I'm working with an EP2C20 dev kit), and I'd like to hear about your experience dealing with the 5V/3.3V conversions, especially the latencies you are seeing.

I think it's a bit over-the-top to do this on a board without a ground plane, good luck, you'll definitely need it.

[tnt23]

Originally Posted by skan

Sounds neat! But I suspect MP3 decoding/encoding is out of the question, right?

OT: tnt23, still working on the "megadrive"?

Rather thinking of FPGA Megadrive incarnation.

A SDRAM board doing mp3 stuff would sound rather crazy would it not?

[tnt23]

Originally Posted by Shadowfire

TNT, if you manage to get the 5V I/O interface up and running, could you please leave a message about what level shifters you are using? I'm prepping for something a bit more... complex than my last project, tentatively looking at the Cyclone EP3C16 (although I'm working with an EP2C20 dev kit), and I'd like to hear about your experience dealing with the 5V/3.3V conversions, especially the latencies you are seeing.

I think it's a bit over-the-top to do this on a board without a ground plane, good luck, you'll definitely need it.

I am going to use QS3245 5V Quickswitch - "5Ω bidirectional switches connect inputs to outputs"
http://www.idt.com/?genId=QS3245
From the datasheet, its data propagation delay is 0.25ns max. I think I also saw Quickswitch series mentioned in some Altera appnotes regarding PCI bus and 5v/3.3v tolerance.

I wish I could use a dedicated ground plane, but four layer PCB would be far too expensive for test project like this I am trying to compensate this with copper power/ground polygons wherever possible.

[skan]

Originally Posted by alexh

Depends on the room in the FPGA. I've done MP3 accelerator functions (pipelined IDCT) for FPGA's before and they are not that big. Both Xilinx and Altera provide free open source MP3 decoders mainly software using one of their soft-CPU's.

Originally Posted by tnt23

Rather thinking of FPGA Megadrive incarnation.

A SDRAM board doing mp3 stuff would sound rather crazy would it not?

Well, I liked the idea anyway!
(beware: I could have said "graphics+audio card on FPGA". Now, what's worse? )

FPGA Megadrive seems the natural evolution to me too. Good!

[Shadowfire]

Thanks for the link! The quickswitches look very promising.

[tnt23]

To sum Z3 timings up, this gives ~95ns minimum for simple read cycle. Provided data are read in 32-bits, this results in ~40 Megabytes per second throughput. (And then there are Multiple Transfer Cycles). What happens in real word? Does someone have any Z3 memory board, like this DKB, to benchmark?

Also, what is this 'caching' mentioned in the specification? Does it mean that even if reading byte or word, the card should always present full 32-bit word?

[alexh]

Originally Posted by tnt23

Does someone have any Z3 memory board, like this DKB, to benchmark?

I have one but how are you going to target memory on this device only?

[tnt23]

Originally Posted by alexh

I have one but how are you going to target memory on this device only?

That's what I was asking here: http://eab.abime.net/showpost.php?p=622827&postcount=24

Can you give the abovementioned test programs a try? The one named 'bustest' probably is able to test selected memory region.

[wawa]

ville9 has published those benchmarks on a1k
http://www.a1k.org/forum/showpost.ph...3&postcount=88

i think pretty understandable also without german knowledge. also there is a whole discussion about a possible zorro ram extention somewhere.

[rkauer]

Hijacking thread a bit: I noticed people used a Radeon card as memory expansion with some grade of success. A bit faster than chip mem, but hey! It is for free!

[alexh]

Hardly free as you need a PCI->Zorro III bridge.

[tnt23]

Originally Posted by wawa

ville9 has published those benchmarks on a1k
http://www.a1k.org/forum/showpost.ph...3&postcount=88

i think pretty understandable also without german knowledge. also there is a whole discussion about a possible zorro ram extention somewhere.

Nice, thanks! Wasn't able to find the discussion though, German is almost unreadable to me

[wawa]

i think it is that:
http://www.a1k.org/forum/showthread.php?t=15503
i am not able to reread it all atm, the conclusion was afair, it is possible to build such a mem expansion, but it wouldnt be faster than about 10mb/s

the forum has english/international section where you might get some help.

also in this thread you can find some memory testing software developed and used by hardies on a1k. try the latest versions. you will have probably to replace *.pdf with *.lha or maybe they are just exe's. never used these myself.
http://www.a1k.org/forum/showthread....memtest&page=6

[tnt23]

Originally Posted by wawa

i think it is that:
http://www.a1k.org/forum/showthread.php?t=15503
i am not able to reread it all atm, the conclusion was afair, it is possible to build such a mem expansion, but it wouldnt be faster than about 10mb/s

Here's what I have found on the net (Dave Haynie regarding Zorro speed, dated 1990). Worth saving anyway!

Well, for timing the maximum theoretical speeds for Zorro III full and
multiple cycles, I simply pulled out "The Zorro III Bus Specification by Dave
Haynie", flip to "Chapter 5: Timing", and add up the various lengths of
different cycle events for each type of cycle. That figure sets the minimum
possible cycle time on the bus, in nanoseconds in this case. A cycle
transfers 4 bytes, so if you know ns/byte, it's easy to find bytes/ns,
and ultimately, megabytes/second. Again, actual Zorro III cycle time is
based on the efficiency of the Zorro III bus master and Zorro III bus slave
acting together.

A 68030 isn't a perfect Zorro III bus master, so you'll find that, for a
given memory chip speed, a 68030 will talk to a 68030 memory design faster
than a Zorro III memory design. It'll be harder or more expensive to build
a Zorro III memory board that'll go 20MB/s with a 68030 (I built one, but
it uses expensive SRAM) than it would be to build a native 68030 memory
board that'll go 20MB/s with a 68030. That's rather common on I/O buses,
and a well designed I/O bus master will be able to drive the Zorro III bus
significantly faster than the 68030, or most any CPU, can.

--
Dave Haynie Commodore-Amiga (Amiga 3000)


Perhaps it will be possible to use higher speed SDRAM (133MHz) or even a DDR /DDR2 memories to achieve minimum access times possible on the bus. Still, even 10mb/s for a Z3 memory seem better than nothing.

also in this thread you can find some memory testing software developed and used by hardies on a1k. try the latest versions. you will have probably to replace *.pdf with *.lha or maybe they are just exe's. never used these myself.
http://www.a1k.org/forum/showthread....memtest&page=6

I will definitely try these, I am going to set up a 4000 next week to start tinkering with the prototype board.

(Psst! Have anyone seen Zetr0 lately?)

[wawa]

ím not quite sure im getting it. zorro ram board made by haynie? ive never heard of a device transferring 20mb/s on zorro3, busmaster or not. not even elbox claims that much for their ide controller, even if it was any close to reality anyway.

but good luck though. the pcb looks shiny indeed!

[aperez]

It seems to me that either replicating the latest Super Buster as a 5V 84-PLCC CPLD would be necessary, given the lack of availability of Zorro III chips these days.

Given that, I've considered putting my time into a replacement Buster that replaces the Zorro bus with PCI.

[tnt23]

Originally Posted by wawa

ím not quite sure im getting it. zorro ram board made by haynie? ive never heard of a device transferring 20mb/s on zorro3, busmaster or not. not even elbox claims that much for their ide controller, even if it was any close to reality anyway.

At least BigRam was developed by Dave. There are a few tips in the BigRam docs regarding possible speed enhancements.

Multiple transfer cycles seem quite promising. I believe most, if not all, designs of the time were based on DRAM with its typical access times of 60-70ns. If you take SRAM with 10-20ns access that'd speed things dramatically.

Besides, Zorro RAM board in theory could master the bus by itself. Don't know if it would be able to DMA local (motherboard) memory though, and it most likely would require a software driver of some sort.

[tnt23]

Originally Posted by aperez

It seems to me that either replicating the latest Super Buster as a 5V 84-PLCC CPLD would be necessary, given the lack of availability of Zorro III chips these days.

Given that, I've considered putting my time into a replacement Buster that replaces the Zorro bus with PCI.

My A3000's Zorro bus now carries Cybervision64, Deneb and Buddha on top of that. (Although Buddha is not a Z3 card.) Not bad for a 'stillborn' bus!

[alexh]

Originally Posted by aperez

It seems to me that either replicating the latest Super Buster as a 5V 84-PLCC CPLD would be necessary, given the lack of availability of Zorro III chips these days.

There are plenty of them around. Commodore reportedly manufactured significantly more Rev9+Rev11 busters than there are A3000/A4000 computers. I think you'd be amazed how may Amiga owners have a Rev9 buster sitting in their drawers cos they upgraded.

[wawa]

Originally Posted by aperez

It seems to me that either replicating the latest Super Buster as a 5V 84-PLCC CPLD would be necessary, given the lack of availability of Zorro III chips these days.

Given that, I've considered putting my time into a replacement Buster that replaces the Zorro bus with PCI.

nice try. i wonder where all that inspiration comes from.. as alexh said there are plenty busters of all sorts flying around. the only reason for a replacement would be to iron out the long known bugs of these chips that have been mostly worked around already anyway. also how do you want to reverse ingeneer? or is there documentation available?