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Old 19 April 2018, 23:18   #3101
8 Bit Dreams
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Quote:
Originally Posted by chue View Post
I will mention one other thing - I am using the industrial version of the CPLDs, because at the time I bought them digikey was out of the commercial version.

https://www.digikey.com/product-deta...982-ND/1957202

I'm not sure if that makes any difference, but I did just order some of the commercial version chips.
i have some industrial grade cpld's here, can try to solder them up @ weekend just to proove this theory..
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Old 19 April 2018, 23:21   #3102
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Interesting... I ordered some of the 1 amp parts and will see if that makes a difference in my current TF530 build.


Not programming is different from not found. It will be soldering related
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Old 19 April 2018, 23:23   #3103
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Not programming is different from not found. It will be soldering related
i'm also pretty sure it is a short, trying to explain it to Chue, but he don't belive me for some reason..
maybe it's indeed a faulty cpld...who knows..

Last edited by 8 Bit Dreams; 19 April 2018 at 23:35.
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Old 19 April 2018, 23:41   #3104
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i'm also pretty sure it is a short, trying to explain it to Chue, but he don't belive me for some reason..
maybe it's indeed a faulty cpld...who knows..
Well I will check again with the meter. It won't hurt anything to do so.
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Old 20 April 2018, 08:08   #3105
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Terrible Fire Accelerators

Quote:
Originally Posted by chue View Post
Well I will check again with the meter. It won't hurt anything to do so.

When I have an issue I keep looking until I find it. Get the eagle schematic and trace the power and JTAg pins so you can see where a short might be happening.

Personally I would bet that many of your pins look soldered to the pads but are not

EDIT: simply changing out parts in the hope that you’ll find your issue will not work. You need to try and understand what is happening

Last edited by plasmab; 20 April 2018 at 10:36.
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Old 21 April 2018, 16:40   #3106
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Well you guys were spot on. It came down to dodgy soldering.

I pulled off both CPLDs, cleaned the board and the chips with IPA. I then soldered the chips back on. After that I checked for pin shorts as well as for pins that were not soldered onto the board. I found plenty of the latter, and fixed those.

After all that I plugged it in, and viola - it worked! I was able to identify and program both chips.

Now I have to do the RAM chips, and then some through hole stuff (68K connector, IDE, SPI, 68030 socket, FPU socket). I am excited!
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Old 21 April 2018, 17:43   #3107
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Originally Posted by chue View Post
Well you guys were spot on. It came down to dodgy soldering.

I pulled off both CPLDs, cleaned the board and the chips with IPA. I then soldered the chips back on. After that I checked for pin shorts as well as for pins that were not soldered onto the board. I found plenty of the latter, and fixed those.

After all that I plugged it in, and viola - it worked! I was able to identify and program both chips.

Now I have to do the RAM chips, and then some through hole stuff (68K connector, IDE, SPI, 68030 socket, FPU socket). I am excited!
good stuff!
come back with this soon:



Last edited by 8 Bit Dreams; 21 April 2018 at 18:15.
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Old 21 April 2018, 18:26   #3108
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I have spent time today bullet proofing the TF534 bus cpld. I think I’m nearly there.
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Old 21 April 2018, 19:06   #3109
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good stuff!
come back with this soon:




Those numbers don’t look like TF 530 numbers. Is that Matze’s TK?
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Old 21 April 2018, 19:23   #3110
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Those numbers don’t look like TF 530 numbers. Is that Matze’s TK?

Agreed. 20 mips is the most I ever saw in sysinfo.. at 56mhz.
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Old 21 April 2018, 19:51   #3111
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Agreed. 20 mips is the most I ever saw in sysinfo.. at 56mhz.
Yeah, guys, i was cheating here, sorry
it's Matze's TK installed in my A2000 with 4MB Zorro II card..
have finished to build RAM part yesturday, doing testing phase now with A500, A1000 and A2000. All looks good, no graphic issues on A2000. it runs with 1 waitstate for IDE and 0 waitstates for RAM.

wanted to give Chue some motivation
PS
@Chue
You can even start Your TF card without RAM soldered on, it will report Zorro Card error, just skip it and try to boot form IDE

PPS
can't wait to build up a TF534!

Last edited by 8 Bit Dreams; 21 April 2018 at 19:59.
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Old 21 April 2018, 20:02   #3112
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Yeah, guys, i was cheating here, sorry
That’s a nice card, but something really has to be said for TF530 remaining 2-layer. The TK is somewhat expensive to make (and large!)

@plasmab
I just watched a good portion of a video looping Frontier. Where was this corrupted text?
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Old 21 April 2018, 22:04   #3113
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That’s a nice card, but something really has to be said for TF530 remaining 2-layer. The TK is somewhat expensive to make (and large!)

@plasmab
I just watched a good portion of a video looping Frontier. Where was this corrupted text?
Look at the text on the frontier menu and credits... they flicker with single character corrupted text. This issue is now solved.
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Old 22 April 2018, 11:52   #3114
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@Chue,
with this message i confirm industrial grade cpld's are fully working on TF530, have just built one board using them, runs more than 1 hour without any bugs

PS
can someone point me please where can i learn about vhdl in easy way? i am asking cause i'm sitting on a banch of 7ns Xilinx chips im unable to use, someone told me changing acess time is dead easy, wanna find out how is it doable and give it a try. Also want to understand more about programming cpld's..
regards,

Viktor
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Old 22 April 2018, 13:28   #3115
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@Chue,
with this message i confirm industrial grade cpld's are fully working on TF530, have just built one board using them, runs more than 1 hour without any bugs

PS
can someone point me please where can i learn about vhdl in easy way? i am asking cause i'm sitting on a banch of 7ns Xilinx chips im unable to use, someone told me changing acess time is dead easy, wanna find out how is it doable and give it a try. Also want to understand more about programming cpld's..
regards,

Viktor
In ISE Project Navigator open both your .xise files (mux/ram) and right-click the chip in the Hierarchy -> 'Design Properties', now in the 'Project Settings' Pane there should be 'Speed' on the drop down select -7.

Also regarding Timing Constraints, you may have to adjust them in the Tools->Constraints Editor, in which case based on the generated Timing Report generate by right-clicking on 'Optional Implementation Tools -> Generate Timing' and clicking 'rerun / rerun all' after which take time to study the report which you should then be able to work out how much delay or less delay to 'Period' of CLKCPU adjustable in the Constraints Editor OR by text editing the .ucf file.

Last edited by solidcore; 22 April 2018 at 13:35.
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Old 22 April 2018, 13:30   #3116
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In ISE Project Navigator open both your .xise files (mux/ram) and right-click the chip in the Hierarchy -> 'Design Properties', now in the 'Project Settings' Pane there should be 'Speed' on the drop down select -7.
Thank You mate!
will try, and report back!
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Old 22 April 2018, 14:58   #3117
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OK i have spent alot of time this weekend on the TF534.

The bus CPLD i have got working solid but the RAM cpld is not working properly. I setup the ram cpld to hold all its bus lines high and they wobble enough to cause the bus cpld to think there are bus requests coming from it.

I then swapped all the parts back onto my TF534S and they work fine there. So no bloody clue whats wrong. TF534 rev 2 is a dud basically.
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Old 22 April 2018, 16:13   #3118
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TF534 rev 2 is a dud basically.

Please don't give up, Stephen!
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Old 22 April 2018, 16:59   #3119
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OK i have spent alot of time this weekend on the TF534.

I then swapped all the parts back onto my TF534S and they work fine there. So no bloody clue whats wrong. TF534 rev 2 is a dud basically.
Sounds like it’s time to put this project aside for a while. Go have a pie (reference to one of the MIB movies) and you’ll probably figure it out.
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Old 22 April 2018, 17:45   #3120
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Sounds like it’s time to put this project aside for a while. Go have a pie (reference to one of the MIB movies) and you’ll probably figure it out.
I've not spent very much time in the last three weeks on this but I managed to prove today that the cpld does not run stable. When i assert my inter CPLD signals as a logic high with nothing else programmed in the cpld the other cpld reads this randomly as a 1 or a 0. I traced this down to a massive wobble on the CPLD power line.

At first i thought it was the regulator so i removed the regulator and powered the 3.3v rail from one of my 6632B power supplies. but still the wobble is there.

Either the CPLD is not decoupled enough or i have bad wiring. Essentially its an electrical problem this time not a firmware one.

EDIT: I have built 2 boards with absolutely identical wobbles on the power lines.
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