15 September 2017, 16:51 | #21 | |
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Quote:
Hmm, I wonder if the problem has something with: "- Final MSVC 2017 compiled". (because it doesn't happen on newer CPU - as Toni probably have!?) |
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15 September 2017, 16:55 | #22 | ||
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Does softfloat mode crash identically? Quote:
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15 September 2017, 17:01 | #23 | |
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(hmm, so just wonder how is that possible) Can you try to test again with configuration I used in post #18 !? (In the zone.) (In df0 mount WB3.1 and as HD archive mount the demo file - start the demo from workbench) Last edited by amilo3438; 15 September 2017 at 17:07. |
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15 September 2017, 17:07 | #24 |
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15 September 2017, 17:28 | #25 |
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With my test configuration:
- If "FPU support" is off = get guru 8000 0006. - If "FPU support" is off but Softfloat is on = it works fine. Tested in 3600b4. (get same also if tested on the 1st problematic WinUAE 3.4.1b3 2017.03.13) Last edited by amilo3438; 15 September 2017 at 17:42. |
15 September 2017, 18:03 | #26 |
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Could there be a faulty part of the FPU code affecting the 3D animation (jumping around the screen) and causing the crash at the tunnel? This whole situation reminds me of the Pentium FDIV bug.
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15 September 2017, 18:15 | #27 | |
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In Windows calculator my cpu pass the test. |
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15 September 2017, 18:24 | #28 |
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I passed the test too. I just thought the situation was similar: a bug in floating-point code.
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15 September 2017, 19:11 | #29 |
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Code:
HH D0 00000068 D1 00000000 D2 00000002 D3 00000008 D4 00000022 D5 00000020 D6 0000000A D7 4741C3FC A0 47456EA4 A1 4755BB98 A2 47CACFF8 A3 47CACBF8 A4 47454220 A5 4741708C A6 47C9D1F8 A7 4742080C USP 4742080C ISP 00202350 SFC 00000000 DFC 00000000 CACR 00002111 VBR 00000000 CAAR 00000000 MSP 00000000 T=00 S=0 M=0 X=0 N=0 Z=0 V=0 C=0 IMASK=0 STP=0 0: 400F-FC42DE9C-EE7A2000 #1.291577e+05 C00F-B7160000-00000000 #9.374000e+04 2: FFFF-7FFFFFFF-FFFFF800 -nan FFFF-7FFFFFFF-FFFFF800 -nan 4: FFFF-7FFFFFFF-FFFFF800 -nan FFFF-7FFFFFFF-FFFFF800 -nan 6: FFFF-7FFFFFFF-FFFFF800 -nan FFFF-7FFFFFFF-FFFFF800 -nan FPSR: 00000080 FPCR: 00000090 FPIAR: 009fae1e N=0 Z=0 I=0 NAN=0 Prefetch 47449110 15812800 (1) e6a1 (1) 1581 (1) 2800 (1) 4744910C 6de4 BLT.B #$e4 == $474490f2 (F) <-- demo code D0 FFFFF0C1 D1 00000004 D2 00000000 D3 00000000 D4 00000000 D5 FFFFFFFA D6 00000000 D7 8000000B A0 00000104 A1 00000000 A2 474665E0 A3 00000000 A4 474665E0 A5 00202308 A6 FBE90779 A7 00202308 USP 4742079C ISP 00202308 SFC 00000000 DFC 00000000 CACR 00002111 VBR 00000000 CAAR 00000000 MSP 00000000 T=00 S=1 M=0 X=0 N=0 Z=0 V=0 C=0 IMASK=7 STP=0 0: 4002-C0000000-00000000 #1.200000e+01 0000-00000000-00000000 #0.000000e+00 2: 3FFF-E7DFD700-00000000 #1.811519e+00 C00F-9036587D-82A55000 #7.383669e+04 4: 3FFF-A0000000-00000000 #1.250000e+00 4000-80000000-00000000 #2.000000e+00 6: C000-B2B22ECA-62213800 #2.792125e+00 BFF9-9A563692-94459000 #1.883994e-02 FPSR: 04000088 FPCR: 00000090 FPIAR: 4744be44 N=0 Z=1 I=0 NAN=0 Prefetch 009fd844 fff63039 (2) fff6 (1) 3039 (1) fff6 (1) 009FD842 51c8 fff6 DBF .W D0,#$fff6 == $009fd83a (F) <-- reloc OS39 EXEC 45.20 D0 00000002 D1 00000020 D2 00000000 D3 00000000 D4 00000000 D5 FFFFFFFA D6 00000000 D7 0000E490 A0 00DFF000 A1 00000000 A2 474665D0 A3 00000000 A4 474665D0 A5 00000000 A6 01FF0D8F A7 00202320 USP 47421354 ISP 00202320 SFC 00000000 DFC 00000000 CACR 00002111 VBR 00000000 CAAR 00000000 MSP 00000000 T=00 S=1 M=0 X=0 N=0 Z=0 V=0 C=0 IMASK=7 STP=0 0: 4002-C0000000-00000000 #1.200000e+01 0000-00000000-00000000 #0.000000e+00 2: 3FFF-E7DFD700-00000000 #1.811519e+00 C00F-9036587D-82A55000 #7.383669e+04 4: 3FFF-A0000000-00000000 #1.250000e+00 4000-80000000-00000000 #2.000000e+00 6: C000-B2B22ECA-62213800 #2.792125e+00 BFF9-9A563692-94459000 #1.883994e-02 FPSR: 04000088 FPCR: 00000090 FPIAR: 4744be34 N=0 Z=1 I=0 NAN=0 Prefetch 04754004 00000000 (1) 0000 (1) 0000 (1) 0000 (1) 04754000 0000 0000 OR.B #$ff,D0 <-- non-mapped mem. freerun Code:
d 474490f2 474490F2 7200 MOVE.L #$00,D1 474490F4 1233 2800 MOVE.B (A3, D2.L*1, $00) == $00000000 [00],D1 474490F8 4c00 1800 MULL.L D0,D1 474490FC 7608 MOVE.L #$08,D3 474490FE e6a1 ASR.L D3,D1 47449100 1581 2800 MOVE.B D1,(A2, D2.L*1, $00) == $474665d0 [00] 47449104 5282 ADD.L #$01,D2 47449106 0c82 0000 0400 CMP.L #$00000400,D2 4744910C 6de4 BLT.B #$e4 == $474490f2 |
16 September 2017, 11:34 | #30 |
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Please explain..
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16 September 2017, 14:50 | #31 |
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These are the crash triggering events.
This is a cut from StingRay's snippet: Code:
47449A3C f200 00a0 FDIV.X FP0,FP1 47449A40 4cf7 000b 5806 MOVEM.L (A7, D5.L*1, $06) == $474206d8,D0-D1/D3 47449A46 2c71 1400 MOVEA.L (A1, D1.W*4, $00) == $474693d8 [00000000],A6 47449A4A 2401 MOVE.L D1,D2 47449A4C 3ccb MOVE.W A3,(A6)+ [0000] 47449A4E e180 ASL.L #$08,D0 47449A50 3cc3 MOVE.W D3,(A6)+ [0000] Then successive (A6)+ cover chip ram with some A3/D3 values (repeating). Usually (on my config.) the loop is over and the crash is in another loop (see my previous message), depends on scan lines remaining to VBL. At this point the memory is corrupted and the VBL Exec code scheduler grab A5=$0 and jmp to chip RAM. After some instruction an illegal is encountered, vector table is corrupted from previous write and jmp to non-mapped ram (and a freerun start..). I did not check why D1 got a negative and makes all the successive issues. Last edited by ross; 14 November 2017 at 22:54. |
16 September 2017, 15:55 | #32 |
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Well, there isn't to much FPU instructions in loop, only a few
FMOVEand FDIV.X fp0,fp1 so the problem highly likely to be here Last edited by ross; 14 November 2017 at 22:54. |
16 September 2017, 19:48 | #33 |
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I can duplicate this, I just misunderstood what "tunnel sequence" means..
Seems to be rounding related as usual and there is again some native/6888x difference (there is always some differences). |
16 September 2017, 20:50 | #34 |
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Sorry, my bad, I didn't describe more precisely, seeing as there's a few tunnel sequences of different kinds in the whole demo. I meant the large blue tunnel with the quotation at the beginning, right after the title screen.
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19 September 2017, 18:30 | #35 |
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Any fixes yet?
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20 September 2017, 21:23 | #36 | |
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Quote:
I logged FDIV values and compare native vs softfloat. Very first FDIV in above loop had totally different second parameter (100x+ larger) in native mode. No. And so far it seems there is nothing obvious to fix without breaking other programs. Rounding/precision modes have always been problematic when using native FPU via C functions because it can't match real 6888x. For some strange reason it is mainly few demos that fail.. |
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20 September 2017, 21:32 | #37 | |
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Quote:
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22 September 2017, 21:37 | #38 |
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Problem found. Some C-library trigonometric functions return bogus values if FPU rounding mode is not round to nearest.
Demo uses fsin and fcos to calculate some tables and cos() returned something totally wrong. |
22 September 2017, 21:53 | #39 |
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Cool! So it'll be working again by 3.6.0? At least you tracked down the problem, your hard work is much appreciated.
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24 September 2017, 17:01 | #40 |
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Of course it will be in next version
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