Blitter hidden details from chip schematics

[Toni Wilen]

It finally happened!

I got some schematics... Don't ask me. Someone else might tell you. No download talk here. Thanks in advance.

Some quick notes that might interest others

Blitter cycle diagram logic:

Blitter has 4 stage shift register with 2 switchable shortcut connections.
When blitter starts, single one bit is inserted in shift register. Every blitter cycle will advance it by one stage (or two if optional shortcut connection enabled).
When bit shifts back to first stage, it also decreases blitter width counter by one (and every time width counter underflows, width gets reloaded and height counter gets decreased by one)

NOTE: this is simplified.

  /-1-\   /-2-\
A - B - X - Y - OUT

A: Always A channel. Idle cycle if !BLTCON0(A)
B: Always B channel. Skipped if !BLTCON0(B) (Shortcut connection 1 active).
X: Can be C or D or fill mode idle cycle.
Y: D or skipped.

OUT: connects to blitter width counter decrement logic and loops back to A if blit didn't finish. Also is part of D DMA enable select logic.

Normal mode:

If BLTCON0(C) AND !BLTCON0(D): X=C, shortcut connection 2 is active.
If !BLTCON0(C) AND BLTCON0(D): X=D, shortcut connection 2 is active.
If !BLTCON0(C) AND !BLTCON0(D): X=idle cycle, shortcut connection 2 is active.
If BLTCON0(C) AND BLTCON0(D): X=C, Y=D

Fill mode extra special case:

If BLTCON0(D) and !BLTCON0(C): Add extra idle cycle. X=idle cycle,Y=D

Line mode:

Line mode enables shortcut connection 2. Which means normal line mode cycle sequence is actually AX times two. B enable shortcut connection still works normally.
Line mode also disables all channels' normal modulo handling and +2/-2 increment/decrement after channel's DMA access.

The most interesting special case in line mode:

Line mode cycle diagram when blitter width counter != 1: X=C
Line mode cycle diagram when blitter width counter == 1: X=D

This very simple logic explains almost all known line mode side-effects. For example why width needs to be 2 and weird behavior if blitter width is not 2 (if 1: -D-D-D, if for example 3: -C-C-D-C-C-D), or what happens if B channel is enabled (B does normal DMA fetches, -BC-BD-BC-BD).

BLTCON1 OVF bit (documentation only says it should be cleared): This seems to be tell the blitter if shift A value wrapped around (line's horizontal pixel position) = CPT should be increased/decreased by 2 during next C DMA read. Not sure why it is even user settable. (Test case: does line start horizontally 1 word early/late if this bit is set when starting line mode blit)

Channel DMA enable selection logic:

Ae: if BLTCON0(A)=1 AND A=1
Be: if BLTCON0(B)=1 AND B=1
Ce: if BLTCON0(C)=1 AND C=1
De: if BLTCON0(D)=1 AND OUT=1 AND Ae=0 AND Be=0 AND Ce=0

Note that if A/B/C are active simultaneously (see below), only one channel still gets selected, logic currently unknown (seems to be mainly caused by side-effects of used selection logic)

Last D write special case:

OUT goes to separate two stage shift register when blit has finished. Output of this shift register generates enable for last D write.

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Quick (not fully confirmed yet) answers to weird blitter behavior that has been confirmed happening on real hardware if BLTCON0 active channels are changed while blitter is active:

1) shifted one bit can get lost, for example if one bit is in B shift register and if B channel gets disabled. Shortcut connection 1 gets enabled, next blitter cycle will shift bit in B to nowhere because when shortcut connection 1 is enabled, B to X connection is disabled (same for X to Y). Now shift register keeps shifting zero bits only: blitter size register stops decrementing, no channels get selected. Result is active blitter that does nothing useful.

2) shift bit gets duplicated (I am not yet sure whats the condition). In this case channel selection logic gets confused (there is most likely some priority selection due to way logic gates are set up, for example cycle sequence can become BACBAC). One important condition is that D channel is only allowed to be active if all other channels are inactive at the same time. So in many cases D can never be active anymore after shift register has 2 (or more) one bits shifting.

Testing needed to confirm if above assumption is correct:

- more than 1 shifter bit active should also increase rate of blitter horizontal counter decrementing because every shifted one bit out of shift register X or Y (OUT) stage also goes to blitter width counter decrement by one input. Assuming counter can count down every cycle.

- ??


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Wasn't that simpler than expected?


EDIT: schematics apparently can be found from github.com, look out for amiga_replacement_project.

[kamelito]

At last! So in the end where WinUAE emulation stand knowing this?

[Toni Wilen]

Originally Posted by kamelito

At last! So in the end where WinUAE emulation stand knowing this?

Already converted to this logic, obviously (and it does work) Not surprisingly emulation code is now much simpler, less special cases needed.

Undefined behavior is still to do, I haven't had time to do any tests yet.

[Rotareneg]

Did you get schematics for the other chips too?

*edit* Looks like just Agnus/Alice, but still very cool!

[roondar]

That's quite cool, better emulation is always nice and it's super awesome that at least one person now has access to the actual schematics

[jotd]

That wise person gave YOU the schematics after all those years. That's just great!

[TuKo]

Following with lot of interest.

[Toni Wilen]

Shifter one bit going away or duplicating seems to be what really happens.

When blitter is active:

If 1 shortcut connection gets disabled: shifter bit in stage 0 gets copied to both stage 1 and stage 2.

If 1 shortcut connection gets enabled: shifter bit in stage 0 is lost.

If 2 shortcut connection gets disabled, shifter bit in stage 2 gets copied to both stage 3 and OUT.

If 2 shortcut connection gets enabled: shifter bit in stage 2 is lost.

[Rotareneg]

Interesting, on page 8 of the Alice schematics there's some of the mystery UHRES logic.

[bloodline]

Fascinating!!! Thanks for sharing

[Toni Wilen]

Channel selection "priorities" if more than one set bit in shift register:

- C seems to have highest priority. If X or Y has set bit and C channel is enabled: C DMA channel is active.
- A if A has set bit and A channel is enabled (and X and Y are empty = B must have set bit with B channel enabled)
- B only if B channel enabled, A channel not enabled (=A has set bit and B has set bit)
- D is only possible if set bit is in A and A is not enabled.

[bloodline]

Originally Posted by Toni Wilen

Already converted to this logic, obviously (and it does work) Not surprisingly emulation code is now much simpler, less special cases needed.

Hey Toni, let us know when you submit the new code to GitHub! Many thanks for this

[Toni Wilen]

I did say no download talk.. and it was already mentioned in first post..

Anyway, there is clearly visible AGA blitter fix/workaround (it even says "BUSY BUG FIX. DLY 2 CYCLES")

Before AGA, blitter busy was cleared and interrupt generated when last cycle was completed, even if there was last D write still queued in blitter pipeline.

AGA (at least according to schematics) introduced a workaround: if D is enabled and not line mode: add 2 extra blitter cycles before busy is cleared/interrupt generated

This almost surely explains why copper blitter wait fails to work correctly in some specific situations (just exactly "right" DMA contention) but it does not affect AGA.