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Old 18 July 2018, 17:25   #3341
supaduper
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Quote:
Originally Posted by Cobe View Post
I just tried this and when I turn on cd32 without jumper screen stays black and power light dimmed.
then you have an early firmware , you need to update it if you have the programmer tools
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Old 18 July 2018, 20:24   #3342
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Ah..damn...
Thanks for prompt customer support!
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Old 19 July 2018, 23:56   #3343
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So how is it with thw tf328, are there differences in early and late CD32's? Mine is assembled in february 1994 and i was wondering if the tf328 works in it.
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Old 20 July 2018, 06:08   #3344
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Quote:
Originally Posted by Pitka_Masa View Post
So how is it with thw tf328, are there differences in early and late CD32's? Mine is assembled in february 1994 and i was wondering if the tf328 works in it.
In some some very early CD32`s there was a early rom version that can prevent the tf from working but yours will be fine ,there will no problem working with a TF328

Last edited by supaduper; 20 July 2018 at 09:13.
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Old 29 July 2018, 10:41   #3345
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I've been digging through the Xilinx reports generated by the fitter. I then wrote some parsers in python to compare what I expected the pinouts to be vs what Xilinx set them as. There is a mismatch!!

TF530 Rev2
Code:
stephen@debiandev:~/git/tf530/build$ ./validate.py rev2 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 60 PIN: IPL<2> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: IPL<1> UCF: A<13> Error
Checking pin 57 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 UCF: A<13> PIN: IPL<1> Error
Parsing Pinfreeze File: work/ram_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 46 PIN: EXTINT UCF: Error - PIN NOT IN UCF FILE!
TF530 Rev3

Code:
stephen@debiandev:~/git/tf530/build$ ./validate.py rev3 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev3.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 34 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: DSACK<0> UCF: A<13> Error
Checking pin 43 UCF: A<13> PIN: DSACK<0> Error
Parsing Pinfreeze File: work/ram_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev3.ucf .... Done
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Old 29 July 2018, 18:40   #3346
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Does the pinout mismatch issue affect existing firmware (e.g. RC2), or is the issue only present in your unreleased firmware?
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Old 30 July 2018, 23:44   #3347
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Quote:
Originally Posted by chue View Post
Does the pinout mismatch issue affect existing firmware (e.g. RC2), or is the issue only present in your unreleased firmware?
If i understand it correctly - it affects the card itself, as it is routed not like Xilinx expected to be.. Don't know is this causing instabilities though..
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Old 31 July 2018, 21:54   #3348
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Originally Posted by 8 Bit Dreams View Post
If i understand it correctly - it affects the card itself, as it is routed not like Xilinx expected to be.. Don't know is this causing instabilities though..
It will affect all firmwares. I'll recompile them when i get a chance.
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Old 02 August 2018, 23:45   #3349
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Quote:
Originally Posted by plasmab View Post
I've been digging through the Xilinx reports generated by the fitter. I then wrote some parsers in python to compare what I expected the pinouts to be vs what Xilinx set them as. There is a mismatch!!

TF530 Rev2
Code:
stephen@debiandev:~/git/tf530/build$ ./validate.py rev2 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 60 PIN: IPL<2> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: IPL<1> UCF: A<13> Error
Checking pin 57 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 UCF: A<13> PIN: IPL<1> Error
Parsing Pinfreeze File: work/ram_top_rev2.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev2.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 46 PIN: EXTINT UCF: Error - PIN NOT IN UCF FILE!
TF530 Rev3

Code:
stephen@debiandev:~/git/tf530/build$ ./validate.py rev3 | grep -e 'Mismatch\|Error\|bus\|ram'
Parsing Pinfreeze File: work/bus_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_bus_control_rev3.ucf .... Done
Comparing pincounts... Mismatch!
Checking pin 34 PIN: IPL<0> UCF: Error - PIN NOT IN UCF FILE!
Checking pin 43 PIN: DSACK<0> UCF: A<13> Error
Checking pin 43 UCF: A<13> PIN: DSACK<0> Error
Parsing Pinfreeze File: work/ram_top_rev3.gyd .... Done
Parsing UCF File ../ucf/tf530_ram_control_rev3.ucf .... Done
I checked the UCF files/schematic and fitter reports and found something else.

A13 is an unused input and was optimised out by the fitter.
IPL1/2 connect from the 68000 socket to the 68030, not to the CPLD. I removed them.

Comparing the Rev 2 UCF aginast Rev3 and the schematic, I saw the following errors
Code:
Signal   Rev 2 pin     Rev 3 pin  Schematic
AVEC    35                63           35
DSACK0 63             MIA         63
FC0       34               40           34
FC1       33               35           33
After making those edits and adding a timing constraint on the clock from the V2 file, I rebuilt the design and checked the fitter reports against the schematic. Attached is a JEDEC file to program the board, new UCF file, ISE project file and the Verilog source. Can someone try the attached image and report their findings?

Ian
Attached Files
File Type: zip tf530bus_rev3.zip (12.3 KB, 32 views)

Last edited by Stedy; 02 August 2018 at 23:45. Reason: Editing code section
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Old 03 August 2018, 19:13   #3350
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My worry with removing them from the UCF file is that they can get set as ground pins randomly by ISE :/
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Old 05 August 2018, 14:56   #3351
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known working update from Poland
it's 534
https://www.ppa.pl/graffiti/obrazek/...0-4mb-fast-ram
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Old 06 August 2018, 21:29   #3352
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Could someone look at these voltages for me? this will fail " initialize jtag chain " the 68000 socket pins are not soldered in yet I tested the board without the pins. I am using a bench power supply. did not get anything at C2. Thanks
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Name:	tf530-rev3-eeror.png
Views:	54
Size:	719.5 KB
ID:	59138   Click image for larger version

Name:	IMG_2025.JPG
Views:	70
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Old 06 August 2018, 23:18   #3353
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Originally Posted by TimT View Post
Could someone look at these voltages for me? this will fail " initialize jtag chain " the 68000 socket pins are not soldered in yet I tested the board without the pins. I am using a bench power supply. did not get anything at C2. Thanks
1. as for me - it looks like tiny short at the resistor array beneath FPU socket. Take a microscope and have a check
2. You need both CPLD's to be able to program them...
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Old 07 August 2018, 01:05   #3354
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I checked the resistor's, all seem good. I did a " hot pull " of a CLPD and soldered it in. Now it will initialize chain, but can't program them. I did try the bus CLPD only but got errors. I ordered more CLPD'S.. Sorry can't rotate the image.
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ID:	59145  

Last edited by TimT; 07 August 2018 at 01:11.
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Old 07 August 2018, 01:14   #3355
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8 Bit Dreams what soldering tip are you using on the Caps ect..? I am just getting to much solder on the joints. also is there anything better then Alcohol to clean the boards?
Thanks
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Old 07 August 2018, 18:13   #3356
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Quote:
Originally Posted by 8 Bit Dreams View Post
1. as for me - it looks like tiny short at the resistor array beneath FPU socket. Take a microscope and have a check
2. You need both CPLD's to be able to program them...


The short on that resistor array should be ok. It’s all VCC that side of the array
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Old 07 August 2018, 19:26   #3357
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Old 07 August 2018, 19:50   #3358
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I am using same tip as Stephen does, the knife type - building whole board with it. Even CPU socket
Where did You got Your fw? Check it ( there is a good description about FW's few pages back on that thread
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Old 08 August 2018, 01:28   #3359
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Thanks for the info!. after cleaning up the soldering I was able to program the CPLD'S. I tried the Master and Dev versions. I only have a 1000 to test on, it has the Rom mod and works fine. The first time I booted I got blue screen, rebooted then light blue screen... then blank screen. it now has 5v at c2.

Not 100% sure the cpu is good " ebay " or could be the hot pulls. I have other boards and ordered one from plasma. when I get the CPLD'S in I will build another. will not work with DiagROM also.
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Old 08 August 2018, 09:05   #3360
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Quote:
Originally Posted by TimT View Post
Thanks for the info!. after cleaning up the soldering I was able to program the CPLD'S. I tried the Master and Dev versions. I only have a 1000 to test on, it has the Rom mod and works fine. The first time I booted I got blue screen, rebooted then light blue screen... then blank screen. it now has 5v at c2.



Not 100% sure the cpu is good " ebay " or could be the hot pulls. I have other boards and ordered one from plasma. when I get the CPLD'S in I will build another. will not work with DiagROM also.


Stop thinking/assuming everything is broken or you’ll get nowhere. You may just have a data bus short. Check DSACK and AS at the 68000. Erase the ram cpld until you get it booting without it.
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