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Old 30 December 2017, 19:20   #21
ross
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Hi Toni, something broken in a command:
Code:
00020008 >move.l #fffffffe,-(a0)
00020008 213c 7fff ffff           MOVE.L #$7fffffff,-(A0) [aaaaaaaa]
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Old 30 December 2017, 20:08   #22
Toni Wilen
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Fixed. Immediate parsing now uses signed integer only if string starts with '-'.
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Old 12 March 2018, 12:56   #23
ross
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Hi Toni it would be possible to add Copper watchpoints?
Exactly like w command but for Copper: something like
wc x (custom) [value]

(length and RWIFC logically do not make sense with copper).
Can be useful in a myriad of cases where fixing a production regard fixing some race condition between Copper and CPU..

Yes, problem is where to stop, but next the running CPU instruction is good.

Thanks.
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Old 12 March 2018, 13:11   #24
Toni Wilen
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Do you mean detecting copper writes to custom registers? Memwatch points already support it.

w 0 <register> 2 w cop (and others, it looks like channel shortcuts are not listed in help..). Default is CPU.

Note that debugger can only activate between CPU instructions, so actual activation will get delayed if CPU needs to wait for bus cycles.
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Old 12 March 2018, 13:23   #25
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Quote:
Originally Posted by Toni Wilen View Post
Do you mean detecting copper writes to custom registers? Memwatch points already support it.

w 0 <register> 2 w cop (and others, it looks like channel shortcuts are not listed in help..). Default is CPU.
Yes!
Are there any other hidden gems not mentioned in the help?
(maybe I need to dig in history log but is immense!)

Quote:
Note that debugger can only activate between CPU instructions, so actual activation will get delayed if CPU needs to wait for bus cycles.
Absolutely acceptable (use is for CPU/Copper race condition, so is good).

Thanks!
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Old 12 March 2018, 13:31   #26
Toni Wilen
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Code:
static const struct mw_acc memwatch_access_masks[] =
{
	{ MW_MASK_ALL, _T("ALL") },
	{ MW_MASK_NONE, _T("NONE") },
	{ MW_MASK_ALL & ~(MW_MASK_CPU_I | MW_MASK_CPU_D_R | MW_MASK_CPU_D_W), _T("DMA") },

	{ MW_MASK_BLITTER_A | MW_MASK_BLITTER_B | MW_MASK_BLITTER_C | MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F, _T("BLT") },
	{ MW_MASK_BLITTER_D_N | MW_MASK_BLITTER_D_L | MW_MASK_BLITTER_D_F, _T("BLTD") },

	{ MW_MASK_AUDIO_0 | MW_MASK_AUDIO_1 | MW_MASK_AUDIO_2 | MW_MASK_AUDIO_3, _T("AUD") },

	{ MW_MASK_BPL_0 | MW_MASK_BPL_1 | MW_MASK_BPL_2 | MW_MASK_BPL_3 |
		MW_MASK_BPL_4 | MW_MASK_BPL_5 | MW_MASK_BPL_6 | MW_MASK_BPL_7, _T("BPL") },

	{ MW_MASK_SPR_0 | MW_MASK_SPR_1 | MW_MASK_SPR_2 | MW_MASK_SPR_3 |
		MW_MASK_SPR_4 | MW_MASK_SPR_5 | MW_MASK_SPR_6 | MW_MASK_SPR_7, _T("SPR") },

	{ MW_MASK_CPU_I | MW_MASK_CPU_D_R | MW_MASK_CPU_D_W, _T("CPU") },
	{ MW_MASK_CPU_D_R | MW_MASK_CPU_D_W, _T("CPUD") },
	{ MW_MASK_CPU_I, _T("CPUI") },
	{ MW_MASK_CPU_D_R, _T("CPUDR") },
	{ MW_MASK_CPU_D_W, _T("CPUDW") },

	{ MW_MASK_COPPER, _T("COP") },

	{ MW_MASK_BLITTER_A, _T("BLTA") },
	{ MW_MASK_BLITTER_B, _T("BLTB") },
	{ MW_MASK_BLITTER_C, _T("BLTC") },
	{ MW_MASK_BLITTER_D_N, _T("BLTDN") },
	{ MW_MASK_BLITTER_D_L, _T("BLTDL") },
	{ MW_MASK_BLITTER_D_F, _T("BLTDF") },

	{ MW_MASK_DISK, _T("DSK") },

	{ MW_MASK_AUDIO_0, _T("AUD0") },
	{ MW_MASK_AUDIO_1, _T("AUD1") },
	{ MW_MASK_AUDIO_2, _T("AUD2") },
	{ MW_MASK_AUDIO_3, _T("AUD3") },

	{ MW_MASK_BPL_0, _T("BPL0") },
	{ MW_MASK_BPL_1, _T("BPL1") },
	{ MW_MASK_BPL_2, _T("BPL2") },
	{ MW_MASK_BPL_3, _T("BPL3") },
	{ MW_MASK_BPL_4, _T("BPL4") },
	{ MW_MASK_BPL_5, _T("BPL5") },
	{ MW_MASK_BPL_6, _T("BPL6") },
	{ MW_MASK_BPL_7, _T("BPL7") },

	{ MW_MASK_SPR_0, _T("SPR0") },
	{ MW_MASK_SPR_1, _T("SPR1") },
	{ MW_MASK_SPR_2, _T("SPR2") },
	{ MW_MASK_SPR_3, _T("SPR3") },
	{ MW_MASK_SPR_4, _T("SPR4") },
	{ MW_MASK_SPR_5, _T("SPR5") },
	{ MW_MASK_SPR_6, _T("SPR6") },
	{ MW_MASK_SPR_7, _T("SPR7") },

	{ 0, NULL },
};
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Old 12 March 2018, 13:39   #27
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wow, this is a very complete list
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Old 18 November 2018, 13:41   #28
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Hi Toni, I appreciate the memory content displayed by the internal disassembler.
Can be extend to all memory related instructions?

Code:
006CCF74 2c78 0004                MOVEA.L $0004 [002008d4],A6
006CCF78 4279 0012 3456           CLR.W $00123456  <--
---

There are some instructions that I can not direct assemble on debugger, like the Scc family.
Is there any special syntax to use?

Thanks.
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Old 18 November 2018, 14:58   #29
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Done.

CLR added to "allowed to show EA" list. I think it was simply missed, reason is for not trying to decode useless EA for "weirdly" encoded instructions.

Scc (and TRAPcc) work now. Was incorrectly decoded as invalid Bcc/DBcc type instruction.

cc = EQ also works now. Don't just assume any ending "Q" means "Quick"-type instruction.
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Old 18 November 2018, 15:15   #30
ross
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Quote:
Originally Posted by Toni Wilen View Post
Done.

CLR added to "allowed to show EA" list. I think it was simply missed, reason is for not trying to decode useless EA for "weirdly" encoded instructions.

Scc (and TRAPcc) work now. Was incorrectly decoded as invalid Bcc/DBcc type instruction.

cc = EQ also works now. Don't just assume any ending "Q" means "Quick"-type instruction.
Thanks!
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Old 20 November 2018, 14:37   #31
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wow i completely missed this. i had no idea we had a built in assembler since 2017!!!

awesome!
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Old 21 November 2018, 00:35   #32
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Hi Toni, latest winuae.7z:
Code:
0007F052 2d7b 001c                MOVE.L (PC,D0.W,$1c) == $0007f070 [001c00e4],(A6, $001c) == $00000692 [46570000]
0007F056 00e4                     ILLEGAL
Latest official beta is right:
Code:
0007F052 2d7b 001c 00e4           MOVE.L (PC, D0.W*1, $1c) == $0007f070 [0fff0337],(A6, $00e4) == $0000075a [00001ede]
EDIT
Added crash dump, got it with the same latest 'alpha' version
It was really a long time that did not happen to me, occurred during initial hdd loading of my Workbench environment

Yes, a bit random, but maybe it can be of some use
Attached Files
File Type: dmp winuae_4.1.0_b10_2018.11.21_00.48.56.dmp (184.6 KB, 12 views)

Last edited by ross; 21 November 2018 at 02:23.
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Old 22 November 2018, 21:26   #33
Toni Wilen
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It is being rewritten to handle 68020+ addressing mode disassembly correctly. (No, assembly support won't be added that soon)
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Old 22 November 2018, 22:48   #34
ross
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Quote:
Originally Posted by Toni Wilen View Post
It is being rewritten to handle 68020+ addressing mode disassembly correctly. (No, assembly support won't be added that soon)
MOVE.L (PC,D0.W,$1c),(A6,$00e4)
[2d7b 001c 00e4]
is a standard 68k addressing mode.
So there is something wrong here.
Or are you saying that you're working on it and there's still something to fix?

(and no, no request for a 020+ assembly support )
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Old 22 November 2018, 22:56   #35
Toni Wilen
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Yes but (An/Pc,Dx.x,$x) uses same encoding as 68020+ complex addressing modes with some previously undefined bits set.
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Old 24 November 2018, 21:25   #36
ross
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All ok in 4100b11.7z

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