A500 logic analyzer tests

Toni Wilen · 23 May 2008, 20:43

This is probably better forum than uae wishlist..

Attached is first 20 or so DMA access cycles in scanline.

Also regular A->D (70=BLTADAT, 0=BLTDDAT) blit is active at the same time (easy to see free cycles)

3C = Horizontal sync strobe (note long time between strobe and real hsync signal changing state)
Following 3 x 1FE = refresh slot (strobe is first refresh)
26 = disk DMA (x 2, 3rd slot is free. Test was enabled disk write to non-existing disk)
AA,BA,CA,DA = AUDxDAT

Everything matches 100% with diagram in HRM. (so boring.. I'd have expected some differences..)

Only problem is matching VPOSR hpos=0 position. (I'd expect it to be strobe position but it may not be exactly right)

Zetr0 · 24 May 2008, 03:09

Fascinating,

what mischief are you upto Toni?

Photon · 30 June 2008, 17:52

He's making sure the science gets done, like real men do.

Yeah, would have been interesting to see any deviance from HRM, many have claimed to have experienced errors.

Either way, on limited hardware it's crucial for optimum performance to know the exact behavior, not only "how to code this to do that". One example on recent platforms is knowing exact behavior of caches and memory interfaces, now that DMA plays a smaller role.

Gonna write a thread in prb.hardware for a project now

cos I finally got paid...

23 May 2008, 20:43	#1
Toni Wilen WinUAE developer Join Date: Aug 2001 Location: Hämeenlinna/Finland Age: 49 Posts: 26,546	A500 logic analyzer tests This is probably better forum than uae wishlist.. Attached is first 20 or so DMA access cycles in scanline. Also regular A->D (70=BLTADAT, 0=BLTDDAT) blit is active at the same time (easy to see free cycles) 3C = Horizontal sync strobe (note long time between strobe and real hsync signal changing state) Following 3 x 1FE = refresh slot (strobe is first refresh) 26 = disk DMA (x 2, 3rd slot is free. Test was enabled disk write to non-existing disk) AA,BA,CA,DA = AUDxDAT Everything matches 100% with diagram in HRM. (so boring.. I'd have expected some differences..) Only problem is matching VPOSR hpos=0 position. (I'd expect it to be strobe position but it may not be exactly right) Attached Thumbnails

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24 May 2008, 03:09	#2
Zetr0 Ya' like it Retr0? Join Date: Jul 2005 Location: United Kingdom Age: 49 Posts: 9,768	Fascinating, what mischief are you upto Toni?

30 June 2008, 17:52	#3
Photon Moderator Join Date: Nov 2004 Location: Eksjö / Sweden Posts: 5,647	He's making sure the science gets done, like real men do. Yeah, would have been interesting to see any deviance from HRM, many have claimed to have experienced errors. Either way, on limited hardware it's crucial for optimum performance to know the exact behavior, not only "how to code this to do that". One example on recent platforms is knowing exact behavior of caches and memory interfaces, now that DMA plays a smaller role. Gonna write a thread in prb.hardware for a project now cos I finally got paid...

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