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Old 02 April 2012, 15:35   #81
Chain
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as i thought, it will not be that easy
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Old 04 April 2012, 01:20   #82
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If you have already built the original circuit, try to add the 74HCT14 between gary and the circuit, should work much better.

See attached file for my connections.
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Old 05 April 2012, 07:40   #83
Chain
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Ive done it only on solderless breadboard, and im lazy bum, so uploadin whole eagle project will be VERY appreciated
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Old 05 April 2012, 09:20   #84
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Ok I'll finish the latest layout and upload it when ready.
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Old 05 April 2012, 15:22   #85
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Okay... so can anyone provide me with a working schematic to do this hack? I would like to have 1MV chip on rev6a motherboard AND a usable trapdoor slot for KCS Power PC board.
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Old 17 April 2012, 12:11   #86
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Picture of latest version, I'll try it later today.

Using a Maxim DS1xxxx delay line instead of a HCT14 would result in a much cleaner layout.


edit: Works like a charm. I'll clean the eagle files up a bit, start a version with a Maxim DS1 delay line (less stuff). SMD is not for everyone yet.
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Old 18 April 2012, 01:00   #87
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Is is possible to obtain the eagle files from you? I would love to make such board for myself at home.
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Old 16 May 2012, 16:22   #88
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I just noticed that I have a rev 8A.1 board, basically a reduced A500+, in my (KS1.3) A500.
As it has a Fat Agnus 8375, would adding 4 extra ram chips to the empty sockets work as it is, giving it a total of 1Mb chip, or is extra hacks needed ?
Don't want to mess anything up.

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Old 27 May 2012, 07:52   #89
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You need to re-populate the board with a missing TTL chip on the bottom right corner of the mobo and undo two solder pads.

Check BBOAH or AHDB for a close of A500+ board to see what is missing. Just the four RAM chips & the TTL.
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Old 27 May 2012, 11:42   #90
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I already have the ram chips at hand, but not the TTL, so I guess it's not possible without butchering another Amiga.

I'll just keep it the way it is then, thank you very much.
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Old 28 May 2012, 03:40   #91
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looks like some one was lazy on geting a doublesided board
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Old 30 May 2012, 23:45   #92
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I've got 3 A500's at home, two are PAL motherboards and 1 is NTSC, and I'd love to have the 1MB CHIP RAM mod done to all of them, but unfortunately don't know anyone who's handy with a soldering iron. I sure as heck ain't.
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Old 31 May 2012, 01:00   #93
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brett i must advise that if you meke the 1mb ram mod and solder the modules and retrace lines you won´t be able to use expansion ram modules they won´t be assumed by system
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Old 31 May 2012, 02:26   #94
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Nah, I wasn't going to do it the hard way, I was just going to have the A500's trapdoor RAM be remapped as CHIP. I had an A500 back in the day modded like that and it worked well.
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Old 02 June 2012, 14:53   #95
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Originally Posted by rampartsagain View Post
brett i must advise that if you meke the 1mb ram mod and solder the modules and retrace lines you won´t be able to use expansion ram modules they won´t be assumed by system
As far as I know, not exactly true.

The 1Mb CHIP RAM hack will render only the trapdoor expansion modules ineffective (the memory called RANGER memory, or SLOW FAST RAM). This memory is mapped in 0xC00000 address.

Just some programs (demos, AFAIK) are hard coded to run in this area.

FAST memory (used on the 68k expansion slot on the left side of the Amiga) should not be affected, unless you apply some weird hacks to reactivate the RANGER Memory.

The hack discussed here, if I understand correctly, will correctly reinsert the trapdoor memory into the 0xC00000 address *without* side effects on the FAST memory expansion, making everybody happy.
 
Old 02 June 2012, 15:28   #96
rampartsagain
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well never heard of that hacks but when i done the mod on a spare a500 board ,the expansion card was never detected under workbench.
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Old 01 November 2012, 00:09   #97
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I've just done some observations of the DBR* and RAS0/1 using a logic analyzer and the DBR* signal goes low before the RAS-lines, and goes high again long before the RAS-lines do, just as hemiyoda observed.

So a fix is needed to get this hack to work reliably, but I think a SR-latch to keep the DBR* signal low until the memory cycle completes is probably a better (and simpler!) solution than a delay-line.
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Old 05 November 2012, 10:57   #98
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well, we can even use some PIC for that
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Old 06 November 2012, 14:41   #99
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It's just that the propagation delay on the RAS-signals must be kept to an absolute minimum.
That's also why "74F"-logic should be used, or even better, a fast PAL or GAL.
I intend to try and implement this using a CPLD, if I get the time...

Anyway, here is a variation of the hack, with a SR-latch instead of the delay line:
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