Are "memory barriers" needed with GCC?

[deimos]

Of late I've grown increasingly suspicious that the enabling and disabling of interrupts around the sensitive parts of my code wasn't working as expected. Looking into it, GCC is happy to rearrange bits of code as it sees fit, the only real exception being accesses to things marked volatile, which it will keep in order (relative to other volatile things).

So, if I have code like:

    extern volatile struct Custom * custom;

    ...

    custom->intena = INTF_INTEN;
    Event * event = (Event *) Queue_Dequeue(&eventQueue);
    custom->intena = INTF_SETCLR | INTF_INTEN;

Do I need to add GCC Memory Barriers:

    asm volatile ("" ::: "memory");

around the call to Dequeue?

Edit: The answer is "Yes".

[deimos]

Just found this: https://gcc.gnu.org/onlinedocs/gcc/Volatiles.html

Accesses to non-volatile objects are not ordered with respect to volatile accesses. You cannot use a volatile object as a memory barrier to order a sequence of writes to non-volatile memory. For instance:

int *ptr = something;
volatile int vobj;
*ptr = something;
vobj = 1;

Unless *ptr and vobj can be aliased, it is not guaranteed that the write to *ptr occurs by the time the update of vobj happens. If you need this guarantee, you must use a stronger memory barrier such as:

int *ptr = something;
volatile int vobj;
*ptr = something;
asm volatile ("" : : : "memory");
vobj = 1;

Which seems to back up what I'm saying, even if I can't pinpoint it in my compiled code.