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Old 25 October 2017, 23:09   #1
PR77
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Amiga 500 68K Accelerator - DIY

I'm new here so go easy, especially if my questions have been asked heaps of times. I have searched but come up empty handed with solid info.

Some time back (like 10 years ago) I sourced a bunch of 68000HC12 16MHz DIP64 CPUs, ALTERA / XILINX CPLD and some reasonably fast SRAMs (DRAM or alike is not in my project scope). I'm sure you can see where I am going with this!

Anyway, I have bundled together some Verilog to Autoconfig FastRAM (easy part) but I am battling with the CPU side of the design. Anyone know of an open design (sure I can buy one, but it is so much more rewarding to built it) or who's brain I can pick?!?

Thanks!
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Old 25 October 2017, 23:24   #2
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https://github.com/terriblefire

Maybe?
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Old 26 October 2017, 07:03   #3
PR77
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Quote:
Originally Posted by talybont View Post
I have looked into this a fair bit actually. It is a reference for he Gayle design as I also want to add IDE, however the bus arbitration between the 020 and 000 are different. In my case I am using the same processor. The concept is the same nevertheless; Amiga cycles are slowed (with DTACK) and synchronized with E however local CPU cycles and FastRAM (asynchronous) are fast.
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Old 11 December 2017, 13:44   #4
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Been some progress here. Waiting on PCBs to arrive (OSH Park so coming from the US). Will post the schematics, pcb layout and verilog soon.

I have taken the approach of a "breadboard" PCB design so only the A[] and D[] lines are tracked through. Everything else is jumpered. @14 or 28 MHz I consider such frequencies to be low enough to be OK (I was running the DPI of a Raspi to a TTL LCD via quality jumper wires at 32MHz pixel clock and it was OK).

P.S., I have another idea of a SRAM based Kickstart chip using a small micro to load (from a serial flash) a kickstart image into a SRAM and have the serial flash updateable via the amiga. Micro would hold gary in reset until SRAM is loaded. CPLD and a couple of shift registers to do the A[], D[] and control should suffice. 512Kbytes on a 20MHz AVR should be pretty quick!
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Old 11 December 2017, 21:26   #5
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Just received notification my boards have been de-panelised and the shipment process has started! woohoo! Anyway, KiCAD project is attached and the obligatory 3D PCB picture is of course also attached. The PCB _really_ is just a quick wipp up to avoid wire-wrapping or soldering lots and lots of tiny wires all over the place on some vero-board.

I will prove out the logic then route another PCB. My target is to actually have the board more-or-less the same size as the 68K. The CPLD board I am using is the Dangerous Prototypes CPLD Breakout with the 9572XL. I decided not to use the CPLDs I have as they are too old and don't want to design myself into a corner!

Anyway I am open to suggestions and criticisms! Verilog is to come. I would like to clean it up a bit.

P.S., I will be starting off with the Accelerated CPU running sync'ed with the main clock (7MHz XORed with CDAC or directly from the 28MHz OSC). I would like to get the 68K up to the 50+MHz however my CPLD will not have the logic blocks needed to perform the CLK sync'ing on all the control lines. At least that is my though. I have been studying how gary handles the _OVR to force a delay in the _DTACK; of course this is not available on the 68K socket but _DTACK is essentially disconnected so I _could_ do what I like here. I don't think gary counts the 68K S-phases, only the rising edge of _AS for a new bus cycle. Again comments are SUPER welcome here!
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Old 12 December 2017, 20:43   #6
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I know zit about circuitry but if your project allows to enhance A500s with a cheap board then you'll have followers.
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Old 12 December 2017, 21:17   #7
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That's the plan!
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Old 16 December 2017, 22:12   #8
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Ok, so I have completed the Verilog for the Autoconfig FastRAM. Haven't tested as I still haven't received by PCBs. I will run it through the ISE Simulator to test the fundamentals.

In order to keep everything prototype-able I chose DIP everything. On one hand this is great but my CPLDs are only QFP44 on 100mil breakouts. I'm sure you can see where this is going. For proper Autoconfig FastRAM I've just enough pins (I haven't optimised the design - to aid with debugging). I might be able to get the FastRAM and Accelerator logic into one 44pin'er but I may need some help! So I'm open for anyone to review my Verilog.

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Old 17 December 2017, 18:02   #9
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I'll be interested to see how this goes!

PZ.
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Old 02 January 2018, 22:43   #10
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Happy New Year!

With that out of the way and with my PCBs arriving between Christmas and New Years, I finally this evening managed to solder up on of my boards! A couple of pictures are attached.

Focusing on the FastRAM AutoConfig at the moment so I am using the existing SGS 68K processor. Although this would be OK up to 14 or even 16 MHz I will swap over to the MC68000P12 once I move over to the Accelerator portion of the design.

My OSHPark PCB MOQ was 3 so I have 2 PCBs spare. At effectively 33 USD each (gold plated pads which are harder to solder than HAL which will be my next choice) I am happy to part with one to someone in the community who would like to support the open source 68000 Accelerator! PM me if interested with some details.
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Old 05 January 2018, 21:52   #11
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Finally getting somewhere. My Verilog is completely different to what was originally posted (there were some absolute NOOB errors). AUTOCONFIG is now working and correctly mapping 1MB to the baseAddress defined by the KS. However when I link to the FreeMemoryPool (Byte 0: Bit 5 = 1) I get a bunch of access to the baseAddress but then the Amiga simply stays on the "Light Grey" screen colour. There are still CPU cycles so I think my timing for Write Accesses might be wrong.

Anyone know if this is OK for determine if the LDS || UDS are OK to then assert the RAM /WE;

...

wire FASTRAM_WRITE = (FASTRAM_RANGE && (RW == 1'b0) && (writeStable == 1'b1) /*(~LDS || ~UDS)*/);

...

// Generate a Write Stable signal for timing Bus Assertions after UDS || LDS are LOW.
always @(negedge CLK) begin

if ((AS == 1'b0) && (RW == 1'b0) && ((~LDS) || (~UDS)))
writeStable <= 1'b1;
else
writeStable <= 1'b0;
end

...

assign WE_LOW = ~(FASTRAM_WRITE && ~LDS);
assign WE_HIGH = ~(FASTRAM_WRITE && ~UDS);
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Old 06 January 2018, 11:40   #12
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That's right! Now we are talkin! Adding to the freeMemoryPool now works! I'm happy! Now for the Accelerator part to get working.
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Old 06 January 2018, 12:52   #13
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Best person to talk to about 68000 timings is Exxosuk from the Atari ST land. He sells Atari boosters.

https://www.exxoshost.co.uk/atari/last/storenew/

These things are bomb proof because they've been designed to work on the very picky STFM. They wont autoconfig on the Amiga of course. The Autoconfig code from my TF530 & TF328 boards is pretty bomb proof and they're in verilog.

https://github.com/terriblefire/tf328
https://github.com/terriblefire/tf530

There is also an IDE design and clock domain crossing code there.

The issue you will find is you will need to stick a wire over to INT2 on the A500 edge connector (or figure a way round that issue.. i havent yet). And end users screw that up and send their boards back saying they dont work.

If you use my code your project will need to be GPL too.
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Old 06 January 2018, 13:48   #14
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Thanks for the hints. I used your autoConfig verilog as a base to be honest. Plan is to be 100% open source and GPL compliant. Accelerator portion will first be synchronized to be Amiga 28 MHz but the long term plan ts to go asynchronous.
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Old 06 January 2018, 14:37   #15
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Nice project!

Add this to my favorites.
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Old 08 January 2018, 08:40   #16
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@Plasmab,

In one of your videos you mentioned mouse movement glitches. I didn't managed to find the details on what was causing that but have a suspicion with was VMA/VPA syvhronisation with the E-Clock. Is this correct?
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Old 08 January 2018, 16:33   #17
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Quote:
Originally Posted by PR77 View Post
@Plasmab,

In one of your videos you mentioned mouse movement glitches. I didn't managed to find the details on what was causing that but have a suspicion with was VMA/VPA syvhronisation with the E-Clock. Is this correct?


You are reading the chipset too fast. The mouse is Amiga chipset not CIA. Check your DTACK timing
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Old 11 January 2018, 22:11   #18
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Not much to update unfortunately. Waiting on some more CPLDs as the magic smoke seemed to escape the one being used for the accelerator logic. Want to keep the FastRAM one in tack. I think it drove in to a contention and now the VCC and GND are a complete short. To be honest I would have thought the device would have survived. To much other stuff to do I guess and I got sloppy.

New parts should arrive soon.
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Old 17 January 2018, 22:54   #19
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Excellent!

New CPLDs have brought me some luck! Got the next step working. Basic synchronised 14MHz acceleration. With FastRAM I was actually expecting better performance to be honest. Still needs investigation to see if the /DTACK is being in-necessarily delayed.

I got the odd GURU in the FastRAM range so I need to check my calculations for RAM access. I'm using 55ns SRAMs and they might be borderline. Any thoughts community?

Anyways, I'm super happy with this! I promise a GitHub page soon, but I really want to focus on getting the fundamentals up.

>>> I've noticed that now SYSINFO is correctly reporting "Display" as STD DENISE. Some other screen shots AGA LISA CHIP. I have absolutely no idea why... Anyone got a clue?
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Old 18 January 2018, 15:16   #20
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Pr77,

Well done. What resources are you using such as documentation etc for this build?

I am interesting in doing the same sometime probababy with my spare altera fpgas laying around.

Keep us updated !
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