EAB's Build your own Amiga Hardware Project

[Zetr0]

Originally Posted by Calgor

Using a PCMCIA-CF adapter and a 2GB 40MB/s SanDisk Extreme IV CF card, I get ~2.5MB/s using sysinfo on the Amiga 1200. Not sure the theoretical limit, if a hardware guy can answer.

IIRC, on a 1.2GB ATA33 HD using an apollo 060+32mb it would attain 1.6MBs - 1.8MBs so clearly CF is faster than that combination, I am yet to actually test the CF cards on the native IDE, obviously with an accelerator there will be a subtle performance increase, but there is a hardwall of arround the 2MBs on the native IDE as it depends on revision of a1200 mobo, and obviously any accelerator you may have.

[Zetr0]

@all

I am on the hunt for the specifcations / datasheet / schematics for the A1000 mobo, especially for the 96pin adapter

all help greatfully recieved.

[Zetr0]

Hello there forum chummies,

With a BIG thanks to "thor" I have been able to re-work an old design by John Kamchen of Silicon Synapse into a new one in eagle.

The (XTRAM) provides upto 8MB of fast ram for your a500 OR MC68k DIL socketed Amiga (this should work on an a600 using the CPC board).

I have yet to include 11 0.1uf decouplers, but thats not difficult (i will get there unless some one beats me too it LOL)

This is Phase 1 of the A600 Fastmem project: for "Phase 2" I intened to re-engineer this board to a "clip-on" memory upgrade for the A600, from the size availble I will most likely limmit it to only 4MB.

okay without much more ado...

The Eagle board revised (XTRAM)

Skt MC68k 8MB Ram Board. "Thor's Hammer"

composite


silk and pads


top layer


bottom layer


holes and via's


original design schematic (XTRam)


heres how to construct the board (XTRam)
Construction Doc

Heres how to configure the Ram for initilization (XTRam)
Memory Initilization Program

here is the driver for the initializing the RAM
memory driver

here is the project folder for the whole lot including archives
Project Folder

here are the original images from the XTRam project

layout


composite


top layer


bottom layer


I have included these here so if anyone spots any errors that i have made they can either correct them or poke me to get it sorted


Again a HUGE thanks for Thor for helping me out.

[narmi]

I'm planning on making one of those 8MB ram cards too, but I'm going to use a single 8MB 72-pin simm for the DRAM. I bought a few, only $1 each! I still haven't got the other parts yet (logic chips), and I need to find an easy way to make the board autoconfig (not too hard). That will be my next project (current one will be done soon).

[Zetr0]

@Narmi

That indeed would be awesome!!!! and one i would certainly implement for the A600

[thor]

Very nice Zetr0, keep it up. I like the name
Autoconfig would be a nice improvement.

Some sources for Germans:
Segor
Conrad
Reichelt
ELV
Pollin

[DrF]

Great work, I would love something like that. I am guessing it would be cheaper to produce these boards new then buy age old boards from eBay what with prices getting silly?

As well as the ace bonus the board being what you actually want it to be. If the socket for the CPU is the same as the original CPU socket would that mean that you could utilise CPU upgrades too? (Just a thought

[Zetr0]

@DrF

That s a good question,

The XTRam board was specifically designed by John Kamchen to take advantage of certain 741 timming's in conjunction of the 68k moto cpu so insofar as using a cpu upgrade i am not so sure if the timming would be correct or fast enough to refresh the memory.

Another thing about the XTRam is that it take a lot of 5v juice nearly 300ma from what the docs explain so a good clean +5 source it recomended although a good solid contact with the 68k socket should suffice the recomendation of a beefy 150watt + PSU. But thats because the need of the 5volt draw, i think this should easy be powered up by a small Pico or Micro 120 - 200 watt PSU, maybe even an Original XBox PSU.. wich is food for thought.

[DrF]

@Zetr0

I like where this is going and will be following it closely
As for the possibility of CPU upgrades, I am guessing only truely compatible upgrades to the orig. CPU socket would work (14Mhz 68000 maybe?), so no 020s etc.

[Zetr0]

Hello there forum chummies,

I have been working on developing this little monster, based on "Livio Plos" original Schematic of creating safe independent 14Mhz 68k moto. Unlike the brute force method this shouldn`t play up your Floppy drive (not being able to read ahead *hence keeping up*) or doulbing the internal clock speed of the CIA's and hence your serial ports.

the design I have developed need to be ratified, allthough it looks good to me... its late, my eyes are very blurry and have been on this for the last couple of days or so. ... you have been warned!

[Edit]
This prototype does not function, as mentioned later in this thread it requires a small handshake of CPU's. please see this post for more detail http://eab.abime.net/showpost.php?p=363645

this particular version is version 3, I believe it will be a challenge to produce at home, but it should be possible with a LOT of patience and practice. I have another version that would be a lot simpler (and a lot bigger too)

okay heres the goodz:- (click thumbs to enlarge / Download)

Composite


Eagle Board to D/L


Livio Plos Original Schematic (1990)


Components


Data Sheets for the Chips used (u2 - u5)
Click Me to Download

Revised Net List


Signal Net


Original mc68000 14mhz project by Livio Plos(1990)
Click to Download


Wow lots of stuff.. so what does all this do compared to the brute force method? well i chose this project because it has three main sections to the process.

(U4a) prepares the 14Mhz clock for the 68k XOR'ing 7Mhz with the CDAC,
(U2 + U3a) delays to the DTACK signal for correct bus cycle timing
(U5 + U3b) makes the E signal (at 0.7Mhz) and syncronizes properly with the CPU, allowing for a regular cycle use of the 8520

sounds complicated... but not so once you get your head round it. I need to research delay lines, as it would be nice to complete this design with an internal CDAC signal, at the moment this would have to be sourced from pin 36 of the Angus, but with a 35ns delay to the 7Mhz line an apropriate CDAC signal can be produced.

and before you say; I was going to call this board revision the "musashi Turbo" but i was a little concerned if any japanese car manufactures would sue me

anyway i hope its of some use.... next up..... combining this with a memory upgrade for the a600


[Edit]
This prototype does not function, as mentioned later in this thread it requires a small handshake of CPU's. please see this post for more detail http://eab.abime.net/showpost.php?p=363645

[DrF]

VERY nice, I hope you finally get a working design, I just cannot wait

[narmi]

@Zetro: I think your accelerator will need to be a bit more complicated that that, because you are not removing the original CPU. The accelerator has to take over the bus from the original CPU to prevent two devices from driving the bus at the same time (prevents magic smoke from coming out). There is a thread over at amiga.org about building an accelerator.

[Zetr0]

@Narmi

Thanks for the heads up,

from what i can read from the thread and the FRANCES sources and what tail and head i could make of the hayines manual, I am left with some confusion over what Oli_HD mentioned on amiga.org

--------------------------------------------------------------------------------

Q: How do i stop the 68000 from working?
A: Using the HLT pin i can let the other micro get control

--------------------------------------------------------------------------------

Nope, A: request the bus (BR) wait till its granted (BG)
and send a BGACK, the 68000 doesnt do anything and you have the bus.
The Haynie archive has the equations for the fastslot found on the A3/4000 which is:
CBR = ’b’1;
BOSS = BG30 # BOSS & !poweron_reset;
BG = local_card_bg;
BG.oe = BOSS;
BOSS is a private BGAck, CBR is just BR.

from what I understand, the original A500 mod that the developed accelerator was derived from, actuly REMOVES the original processor, this could be a slight overlook, I had mistakenly expected a simple halt tied off either CPU would suffice. clearly this is not the case. However Oli's explanation is a little cryptic so I think it needs a little more explanation, atleast for me...

[narmi]

When you remove the original CPU, then there are no issues with two CPUs trying to control the bus at the same time. However, when there are two CPUs, only one can be in control.

Initially, the original CPU will start up and begin executing code. At the same time, the accelerator board (not the new CPU, just some logic chips) will assert the bus request (BR) signal and wait for the original CPU to assert bus granted (BG). I believe the new CPU should be held in reset until the bus is taken over.

Once this happens, the board asserts bus grant acknowledge (BGACK) and is now in control of the computer. The original CPU will do nothing now. I think you have to assert HLT to the original CPU at this point to keep it from doing anything permanently, then let the new processor come out of reset.

Complicated, isn't it? Keep in mind that I have never designed an accelerator board, I'm just trying to make sense of what Oli posted at A.org.

The equations shown are for programming a PAL to implment the bus takeover. You could also do it with 74xx logic chips.

[gulliver]

What modifications should i need in order to use a 28mhz 68000 cpu much like a Supra Turbo accelerator on an A500 with the Livio Plos accelerator?

[Zetr0]

@gulliver

you would need to double the CLK line from 14Mhz to 28Mhz.

keeping the faith to livio's schematic should keep all the remaing buss timmings okay.

where did you find a 28Mhz 68k moto ?

@Narmi

I could use some help in building a logic circuit for cpu handling... if you get any time .... i seemed to of run out of it at the moment

[gulliver]

@yep i could help you, and you could help me!
I was asking about 28mhz because iwanted to apply an 68030 to the design, not a 68000.
Quote from me on another board:

Re: Accelerator hardware theory

I thought a little more about my A600, my accelerator, and made my own mind about some things:
I hate SMC designs, they are not for hobbysts
I dislike ICs which are not DIL for the same reason
So what the hell was i doing with an A600 in the first place! I will try to find an A500 and continue work with it. It is so much easy to hack! Anyway as i mentioned before it is just a different micro layout, and Schoenfeld is about to sell his own, so i dont want to infringe any damage as little as it coul be, to his company!
I made up my mind: an A500 on-chip accelerator, will fit with no troubles many Amiga models as some of you have stated previously (A2000, A1000, A1500, etc).
I read about the Lucas accelerator and the Frances memory board. Too much interesting mental notes were taken in that process, and i eventually could draw some conclusions about my own project.

Even though, i need some help here!

68000 to 68030 interface:
As stated in the Lucas accelerator project, the idea is to make the 68030 resemble an 68000 at 7mhz to the amiga system bus. However, both microprocessor are not pin to pin compatible and have a few different control signals not to mention speed. So this is the actual challenge!
Differences to be solved:

1- Different clock rates
2- Data and Address signals
3- Bus length,/DTACK vs. /DSACK0 and /DSACK1
4- Byte addressability, /UDS and LDS vs. /DS
5- E clock generation at 1/10th of clock signal (0.7mhz)

The help i need is regarding item number 4. In the Lucas accelerator some PAL equations are mentioned, which i dont understand. However, these signal conversions were done in a PAL, i wish someone could point me in the right direction, so i can make them with 74xxx logic ICs.

I have allready covered all the other items mentioned, i wish you could tell me if there is something else i am missing here!


Thanks

[Zetr0]

@gulliver,

any help you can offer and i would be sincerely in your debt, I have managed to redevelop the board at the moment to provide its own CDAC signal. and in the middle of building the logic up for the BUS HANDLING circuit, but I am also in the middle of decorating my daughters bedroom.... welll at least its paint this time.... and not.... overly pink..... LOL....

insofar as to where you are in your development... its a some what a further than me lol... as far as i can see... 1 different clock rates are treated at different levels by the system. according to Livio's schematic he generates a 0.7 (1/10th) clock signal for proper or stable XOR'ing of the CPU, as far as i am aware no matter the cpu you put on the bus. if the cpu needs anything from the bus it either has to wait for it (oh so slow) or cach what its writting and then just have a write back when the bus is ready (oh so much quicker!) lol..

Data and address signalls, some of these you will need to generate with your own hardware. I believe its very possible to to do this with 74xxx logic but the boards might get HUGE lol... i think when i get to that level., I will post a beginers guild to CLPD ) socketed of course! and at this moment .... i think i need a guide too LOL...

its all fun learning.... it wouldn`t be so bad... but as i paint walls a peachy / salmony type of girly colour..... my mind is constructing logic gates.... hmmm....

anyway its good to have you on board

[Zetr0]

okies kinda need some help with this litte beauty if anyone can confirm it... and maybe suggest an applicable IC i would be very happy. OH YES VERY HAPPY

anyways..... some one please confirm or slap me for being stupid

as i understand it (from a perfectly good explantion by Narmi) to take controll from one CPU and hand it over to another other one needs to

• request the BUS
• wait untill its granted
  • assert hault to the original cpu
  • release the secondary cpu from reset state

so with all that i have put this little logic map thingy...... its been a while so a smidge of help is really appreciated.



Its plain to see that the controlling state is BG ( bus granted ) so its all based on a simple NOT circuit if my logic is correct atleast.

[narmi]

My explanation is not 100% correct. I was just reading the Amiga Hardware Reference Manual which explains the correct way to take over the bus. I'll make a circuit and post it later on. The biggest mistake is asserting HLT to the original CPU, that is not necessary and probably shouldn't be done. The normal use of HLT is in combination with RST during a full system reset.

EDIT: I've attached the schematic. This circuit uses one 74LS00 chip to assert /BR op power up, while keeping the new CPU in reset (via /CPURESET). When the old CPU asserts /BG, /BGACK will be asserted, /BR and /CPURESET will be negated to complete the takeover, and bring the new CPU out of reset. The circuit incorporates a latch to keep /BGACK asserted even after /BG is negated by the old CPU.