Terrible Fire Accelerators - Page 143

kgc210 · 25 February 2018, 18:25

Should be a REV 3, see the extra hole by the SPI port. Also pin 25 on the RAM is connected up.

plasmab · 25 February 2018, 19:13

Quote:

Originally Posted by kgc210

Should be a REV 3, see the extra hole by the SPI port. Also pin 25 on the RAM is connected up.

But there are the old aux pins...

I’ll message James

plasmab · 25 February 2018, 19:24

Got a reply from James.. He's going to open the sources up. He still hasnt tested but thats a better place to start from than reinventing the wheel.

plasmab · 26 February 2018, 00:09

Update: I refactored in a few bits on the TF534... The rev2 will have 4Mb SRAM in ZIII space so no interference with ZII cards, 44pin IDE buffered, burst mode ram and lots of space in the ram cpld for SPI.

EDIT: should be ready to place with DirtyPCBs by the end of the week too.

mattymuc · 26 February 2018, 00:52

Thanx Stephen for this great news!
I hope I can add this to my TerribleFire collection soon

plasmab · 26 February 2018, 09:49

Quote:

Originally Posted by mattymuc

Thanx Stephen for this great news!
I hope I can add this to my TerribleFire collection soon

Also if anyone can find a 2Mb SRAM variant I’ll add support for that. The TF534S used 4 x 1Mb chips.

kgc210 · 26 February 2018, 10:03

Something like https://www.mouser.co.uk/ProductDeta...n6heevgk3Uw%3d

£74.83 for 8MB, although it would be very quick 8MB of RAM.

How feasible would it be to move to TSOP 48?
As these would get you 16MB for £82.32 so for an extra £7.50 you get double the RAM, but it's running at 55ns though.
https://www.mouser.co.uk/ProductDeta...yaFC%2fQAoU%3d

plasmab · 26 February 2018, 10:47

Needs to be 5V or the data bus and address bus will need buffered (takes too much space). I’m planning to use 55ns @ 5V. Once I start using 3.3V CPUs we can use that stuff.

kgc210 · 26 February 2018, 11:01

Ahh thought you had switched to 3.3v with you mentioning 4 x 1MB
I guess the CPLD is to full for extra Chip Selects to stick another 4 Chips on the back?

plasmab · 26 February 2018, 13:03

There is no need for more selects.. there is only space for 4 chips on the board.

plasmab · 26 February 2018, 13:38

I can’t switch to 3.3v until we have a 3.3v cpu

8 Bit Dreams · 26 February 2018, 21:34

Quote:

Originally Posted by plasmab

I can’t switch to 3.3v until we have a 3.3v cpu

Stephen, i have tested that FW You've sent to me:
http://eab.abime.net/showpost.php?p=...postcount=2827
do You have any idea why my Zorro II card isn't working (again)? (Card is working fine on Beta FW)

plasmab · 26 February 2018, 21:39

No idea. Sorry.

plasmab · 26 February 2018, 22:09

Almost there

8 Bit Dreams · 26 February 2018, 22:09

Quote:

Originally Posted by plasmab

No idea. Sorry.

ok..but can You take a look into it, next time You work on firmware, please?

another question:
how will TF530 behave, if another IDE interface is present? (as Zorro II card, for example) will these both work? If yes, wich one will be first then?

Quote:

Originally Posted by plasmab

Almost there

woooow, that was swift routing, indeed!!!
should correct that timestamp to 2018

lol

keith · 26 February 2018, 22:44

Wow that was fast! I just can't wait to get my hands on one, hope the build & bring up goes smoothly!

plasmab · 26 February 2018, 22:50

Quote:

Originally Posted by 8 Bit Dreams

ok..but can You take a look into it, next time You work on firmware, please?

Not until after the 17th of March.

Quote:

another question:
how will TF530 behave, if another IDE interface is present? (as Zorro II card, for example) will these both work? If yes, wich one will be first then?

I cant predict what will happen with zorro IO cards.. I assume the onboard will always be scanned first but the boot device should be set by the boot priority of the devices.

Quote:

woooow, that was swift routing, indeed!!!
should correct that timestamp to 2018

lol

Done. As this buffers the data bus those random glitches should be eliminated and i've also wired up everything so that i can eliminate the INT2 flylead completely this time. D3 from the amiga is "broken" through the RAM CPLD.

plasmab · 27 February 2018, 08:16

The A2000 tf sources... in Altium format for some odd reason... nothing to do with me and untested

https://www.dropbox.com/s/f1ptf9gvcl...a2000.zip?dl=0

kgc210 · 27 February 2018, 09:31

Quote:

Originally Posted by 8 Bit Dreams

another question:
how will TF530 behave, if another IDE interface is present? (as Zorro II card, for example) will these both work? If yes, wich one will be first then?

https://github.com/terriblefire/tf53...ed-on-an-A2000

I have already tested with a IDE4Zorro2 and it doesn't work, even with nothing plugged into the TF530.

8 Bit Dreams · 27 February 2018, 20:08

Quote:

Originally Posted by kgc210

https://github.com/terriblefire/tf53...ed-on-an-A2000
I have already tested with a IDE4Zorro2 and it doesn't work, even with nothing plugged into the TF530.

kgc210,
thanks for this update, however, can You please try to run it with Beta FW (Zorro II cards isn't working on RC series firmware atm)

Quote:

Originally Posted by alenppc

The plain trapdoor ram works fine since it's limited to 512K. This happens using PeteAU's open source 2 MB trapdoor expansion (512K chip + 1.5 MB slow-fast).

i don't know, is it the same issue that prevent Zorro cards to work or is it just another issue CACHE related will see soon

Quote:

Originally Posted by EzdineG

Damn. Using the 4MB "4.12.2017" v42 firmware (source code here) for MKL's 68K RAM module from this page:

http://www.mkl211015.altervista.org/ram68k/

Is this because both are trying to put the RAM in the same place?

[EDIT] If so, is line 169 (last 4 variables) dropping me a hint about the values that need to replace those in 172 to move the address? I don't know this language, but if it's that obvious I might have to dive in. Anyone care to chime in?

Same here - have problems with Zorro config under RC2/2.1, it just doesen't work atm, jut try it under Beta fw

26 February 2018, 00:09	#2844
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	Update: I refactored in a few bits on the TF534... The rev2 will have 4Mb SRAM in ZIII space so no interference with ZII cards, 44pin IDE buffered, burst mode ram and lots of space in the ram cpld for SPI. EDIT: should be ready to place with DirtyPCBs by the end of the week too. Last edited by plasmab; 26 February 2018 at 00:15.

26 February 2018, 10:03	#2847
kgc210 Registered User Join Date: Jun 2016 Location: Stoke-On-Trent, England Posts: 450	Something like https://www.mouser.co.uk/ProductDeta...n6heevgk3Uw%3d £74.83 for 8MB, although it would be very quick 8MB of RAM. How feasible would it be to move to TSOP 48? As these would get you 16MB for £82.32 so for an extra £7.50 you get double the RAM, but it's running at 55ns though. https://www.mouser.co.uk/ProductDeta...yaFC%2fQAoU%3d Last edited by kgc210; 26 February 2018 at 10:15.

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25 February 2018, 18:25	#2841
kgc210 Registered User Join Date: Jun 2016 Location: Stoke-On-Trent, England Posts: 450	Should be a REV 3, see the extra hole by the SPI port. Also pin 25 on the RAM is connected up.

25 February 2018, 19:24	#2843
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	Got a reply from James.. He's going to open the sources up. He still hasnt tested but thats a better place to start from than reinventing the wheel.

26 February 2018, 00:52	#2845
mattymuc Registered User Join Date: Jul 2017 Location: Munich / Germany Posts: 88	Thanx Stephen for this great news! I hope I can add this to my TerribleFire collection soon

26 February 2018, 10:47	#2848
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	Needs to be 5V or the data bus and address bus will need buffered (takes too much space). I’m planning to use 55ns @ 5V. Once I start using 3.3V CPUs we can use that stuff.

26 February 2018, 11:01	#2849
kgc210 Registered User Join Date: Jun 2016 Location: Stoke-On-Trent, England Posts: 450	Ahh thought you had switched to 3.3v with you mentioning 4 x 1MB I guess the CPLD is to full for extra Chip Selects to stick another 4 Chips on the back?

26 February 2018, 13:03	#2850
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	There is no need for more selects.. there is only space for 4 chips on the board.

26 February 2018, 13:38	#2851
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	I can’t switch to 3.3v until we have a 3.3v cpu

26 February 2018, 21:39	#2853
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	No idea. Sorry.

26 February 2018, 22:09	#2854
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	Almost there

26 February 2018, 22:44	#2856
keith Registered User Join Date: Jan 2017 Location: Eastbourne Posts: 88	Wow that was fast! I just can't wait to get my hands on one, hope the build & bring up goes smoothly!

27 February 2018, 08:16	#2858
plasmab Banned Join Date: Sep 2016 Location: UK Posts: 2,917	The A2000 tf sources... in Altium format for some odd reason... nothing to do with me and untested https://www.dropbox.com/s/f1ptf9gvcl...a2000.zip?dl=0

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