Terrible Fire Accelerators

[plasmab]

Originally Posted by PR77

Is the SPI AUTOCONFIG and dasey chained (requesting the KS to map to I/O space) when the TF530 AUTOCONFIGs the FastRAM? I could check the verilog, but will ask first. I would like this for my DIY A500 accelerator I'm working on.

I’m not sure what you mean? The two logical cards are in the TF530 RAM cpld and get configured one at a time.

[PR77]

When I read my post again, it also doesn't make any sense to me... I was in a rush and should have just waited until I got home... Too excited I guess! :P

I see that your TF530 AUTOCONFIGs at base address 0x200000 for the FastRAM but also at 0xE90000 as an I/O board from some of the previous screenshots. I checked the TF530 RAM verilog and can't see this (Github version) so I was wondering if you have implemented in a different version dasey chained config requests using a pseudo /CFGIN and /CFGOUT (as in the "real" 100-pin Zorro II bus).

I too would like to do this and stick an MP3 decoder chip in this space. Perhaps parallel accessed (and SPI) for speed. Another nice addition would be a fast UART or a basic Ethernet controller.

[solidcore]

@Pr77 checked the branches ?

[PR77]

@solidcore, clearly not. Thanks for the hint!

EDIT: That's what I was looking for. I see the Zorro II assigned base address was removed and FastRAM fixed to 0x200000. I guess you were starting to run out of room in the 9572?

[plasmab]

https://github.com/terriblefire/tf53.../ram_top.v#L88

[kolla]

Originally Posted by solidcore

there's SANA II which may help but unsure if that's only OS 3.9.

SANA II goes back to Commodore, so no worries

[8 Bit Dreams]

Originally Posted by plasmab

https://github.com/terriblefire/tf53.../ram_top.v#L88

Nice stream yesturday, Stephen! Your A2000 looks amasing, really nice catch! seems like a Rev.6 to me (not sure).

Just wanna add some words about atx PSU You gonna use:
it may be difficult to find ATX v1.0 with -5v (white wire). This voltage was removed in the later versions of ATX PSU's as absolete, however, the Amiga 2000 uses this voltage for the ZORRO cards, so You will need/like to have it
If you gonna use an ATX power supply without the -5v output you could use a voltage regulator LM 7905 to adjust the voltage from -12v to -5v.

Due to the missing TICK signal you need to move the jumper J300 to the position 2-3 and if you have an Amiga 2000 REV4x you need to move the jumper J34 to the position 2-3.

Hope this will help.

[plasmab]

Originally Posted by 8 Bit Dreams

Nice stream yesturday, Stephen! Your A2000 looks amasing, seems like a Rev.6 to me (not sure).



Just wanna add some words about atx PSU You gonna use:

it may be difficult to find ATX v1.0 with -5v (white wire). This voltage was removed in the later versions of ATX PSU's, however, the Amiga 2000 uses this voltage for the ZORRO cards.

If you gonna use an ATX power supply without the -5v output you could use a voltage regulator LM 7905 to adjust the voltage from -12v to -5v.



Due to the missing TICK signal you need to move the jumper J300 to the position 2-3 and if you have an Amiga 2000 REV4x you need to move the jumper J34 to the position 2-3.



Hope this will help.

Aaarrrrrrrrggggghhhhhh! This is the 80th message I’ve had about the tick. I said I was using one of these

http://www.ianstedman.co.uk/Amiga/de...x_adaptor.html

With an ATX supply.

Will you people quit telling grandma how to suck eggs.

EDIT: It’s what I use on my NTSC A1000.

[8 Bit Dreams]

Originally Posted by plasmab

Aaarrrrrrrrggggghhhhhh! This is the 80th message I’ve had about the tick. I said I was using one of these

http://www.ianstedman.co.uk/Amiga/de...x_adaptor.html

With an ATX supply.

Will you people quit telling grandma how to suck eggs.

EDIT: It’s what I use on my NTSC A1000.

Sorry, didn't knew it

[PR77]

Originally Posted by plasmab

https://github.com/terriblefire/tf53.../ram_top.v#L88

Ive checked both the SPI_Alpha and Dev branches, impressive refactoring and awesome ideas (especially the 6800 module- I will try and apply this to my accelerator even though I'm using a 68000, I've ordered some 68SEC000 so the 6800 interface will need to be emulated).

I see that you are not using bit 3 @ 0xE80002 (chained config request), any particular reason for this?

Additionally, I was having a read of the Hardware and Technical Reference Manuals and I can't really find how the Amiga KS determines the conditions to stop reading from address 0xE80000 during the AUTOCONFIG phase. Does it simply loop through this range until D[15:12] = 0xF (asserted by the bus pulp resistors)? And valid AUTOCONFIG card will not have 0xF in all AUTOCONFIG "rom".

EDIT: Background to my questions are obviously when there are at least 2 Autoconfig devices to have a base address assigned. Ie, FastRAM and a R/W data port(s).

[8 Bit Dreams]

Originally Posted by plasmab

EDIT: It’s what I use on my NTSC A1000.

Hmm.. Never heard You have an A1000.. Does it mean that You will try to let TF530 to work on it some day??

[plasmab]

Originally Posted by PR77

Ive checked both the SPI_Alpha and Dev branches, impressive refactoring and awesome ideas (especially the 6800 module- I will try and apply this to my accelerator even though I'm using a 68000, I've ordered some 68SEC000 so the 6800 interface will need to be emulated).

I see that you are not using bit 3 @ 0xE80002 (chained config request), any particular reason for this?

Additionally, I was having a read of the Hardware and Technical Reference Manuals and I can't really find how the Amiga KS determines the conditions to stop reading from address 0xE80000 during the AUTOCONFIG phase. Does it simply loop through this range until D[15:12] = 0xF (asserted by the bus pulp resistors)? And valid AUTOCONFIG card will not have 0xF in all AUTOCONFIG "rom".

EDIT: Background to my questions are obviously when there are at least 2 Autoconfig devices to have a base address assigned. Ie, FastRAM and a R/W data port(s).

Read the Zorro iii reference manual. The bit is not set because the logical cards aren’t related. It’s nothing to do with chaining

[PR77]

Originally Posted by plasmab

Read the Zorro iii reference manual. The bit is not set because the logical cards aren’t related. It’s nothing to do with chaining

Thanks for the hint, didn't really help so I thought I would give my theory a try and ... well it paid off. I now have 2 IO spaces AUTOCONFIG'ed. Was a lot easier thank I thought actually.

I am now running out of Pterms because for some reason ISE is optimising out "reg" variables if only written too. I haven't yet done the verilog for a read but need these variables for the base addresses of my FastRAM and IO spaces. Do you have a hint to surpresses these optimisations? I have to add a "dummy" read in to the Z2 output term but then I use all the 9572s available Pterms.

I.e., I want this;

assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA && ~&autoConfigBaseIOPortB) ? autoConfigData : 4'bZZZZ;

but have to do this;

assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA) ? autoConfigData : 4'bZZZZ;

[plasmab]

Originally Posted by PR77

Thanks for the hint, didn't really help so I thought I would give my theory a try and ... well it paid off. I now have 2 IO spaces AUTOCONFIG'ed. Was a lot easier thank I thought actually.

I am now running out of Pterms because for some reason ISE is optimising out "reg" variables if only written too. I haven't yet done the verilog for a read but need these variables for the base addresses of my FastRAM and IO spaces. Do you have a hint to surpresses these optimisations? I have to add a "dummy" read in to the Z2 output term but then I use all the 9572s available Pterms.

I.e., I want this;

assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA && ~&autoConfigBaseIOPortB) ? autoConfigData : 4'bZZZZ;

but have to do this;

assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA) ? autoConfigData : 4'bZZZZ;

Thats an awful way to do it.. look at this..

https://github.com/terriblefire/tf53...ev/rtl/mkzorro

It spits out the verilog for the autoconfig.

All HDL compilers will optimize out unused stuff unless you tell them not to.. but how can you even tell? If you're not using the result there is no functional difference.

EDIT: If you're running out of PTerms you're doing it wrong. My code is optimized by hard hard experience for ISE.

[plasmab]

Originally Posted by 8 Bit Dreams

Hmm.. Never heard You have an A1000.. Does it mean that You will try to let TF530 to work on it some day??

Its got faulty RAM. I need to get DiagROm in there but that has been low on my todo list...

[PR77]

Here is the whole thing. Perhaps it helps with the context.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:28:36 11/05/2017
// Design Name: Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
// Module Name: A500_RAM
//
// Designer Name: Paul Raspa
//
// Revision:
// Revision 1.0
// Additional Comments:
// 07/01/2018: Maps 1MByte of FastRAM to AutoConfig location. MID 1977, PID 103
// Due to PIN Count of the VQ44 3 spare pins are available which
// could be used to map an additional 1MByte and control the extra
// /CS of the additional RAM. /OE and /WE can be /OE can be tied
// all together. THIS HAS NOT BEEN TIRED.
// 21/01/2018: Added support for two I/O spaces for Fast Ethernet and MP3.
//
//////////////////////////////////////////////////////////////////////////////////

module A500_RAM(
// Control Inputs

input RESET,
input CLK,
input RW,
input AS,
input UDS,
input LDS,

// Address Inputs
input [6:0] ADDRESS_LOW,
input [23:16] ADDRESS_HIGH,

// Data Inputs / Outputs
inout [15:12] DATA,

// RAM Control Outputs
output CE_LOW, CE_HIGH,
output OE_LOW, OE_HIGH,
output WE_LOW, WE_HIGH
);

reg [2:0] configured = 3'b000;
reg [2:0] shutup = 3'b000;
reg [3:0] autoConfigData = 4'b0000;
reg [7:0] autoConfigBaseFastRam = 8'b00000000;
reg [7:0] autoConfigBaseIOPortA = 8'b00000000;
reg [7:0] autoConfigBaseIOPortB = 8'b00000000;
reg writeStable = 1'b0;

wire AUTOCONFIG_RANGE = ({ADDRESS_HIGH[23:16]} == {8'hE8}) && ~AS && ~&shutup && ~&configured;
wire AUTOCONFIG_READ = (AUTOCONFIG_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire AUTOCONFIG_WRITE = (AUTOCONFIG_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire FASTRAM_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseFastRam[7:4]}) && ~AS && configured[0];
wire FASTRAM_READ = (FASTRAM_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire FASTRAM_WRITE = (FASTRAM_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire IOPORTA_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseIOPortA[7:4]}) && ~AS && configured[1];
wire IOPORTA_READ = (IOPORTA_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire IOPORTA_WRITE = (IOPORTA_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire IOPORTB_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseIOPortB[7:4]}) && ~AS && configured[2];
wire IOPORTB_READ = (IOPORTB_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire IOPORTB_WRITE = (IOPORTB_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

// Generate a Write Stable signal for timing Bus Assertions after UDS || LDS are LOW.
always @(negedge CLK) begin

if (RESET == 1'b0)
writeStable <= 1'b0;
else begin

if ((AS == 1'b0) && (RW == 1'b0) && ((~LDS) || (~UDS)))
writeStable <= 1'b1;
else
writeStable <= 1'b0;
end
end

// AUTOCONFIG cycle.
always @(posedge CLK) begin

if (RESET == 1'b0) begin
configured[2:0] <= 3'b000;
shutup[2:0] <= 3'b000;
autoConfigBaseFastRam[7:0] <= 8'h0;
autoConfigBaseIOPortA[7:0] <= 8'h0;
autoConfigBaseIOPortB[7:0] <= 8'h0;
end else begin

if (AUTOCONFIG_WRITE == 1'b1) begin
// AutoConfig Write sequence. Here is where we receive from the OS the base address for the RAM.
case (ADDRESS_LOW)
8'h24: begin

if (configured[2:0] == 3'b000) begin
autoConfigBaseFastRam[7:4] <= DATA[15:12]; // FastRAM
configured[0] <= 1'b1;
end

if (configured[2:0] == 3'b001) begin
autoConfigBaseIOPortA[7:4] <= DATA[15:12]; // IO Port A
configured[1] <= 1'b1;
end

if (configured[2:0] == 3'b011) begin
autoConfigBaseIOPortB[7:4] <= DATA[15:12]; // IO Port B
configured[2] <= 1'b1;
end
end

8'h25: begin
if ({configured[2:0] == 3'b000}) autoConfigBaseFastRam[3:0] <= DATA[15:12]; // FastRAM
if ({configured[0] == 1'b1}) autoConfigBaseIOPortA[3:0] <= DATA[15:12]; // IO Port A
if ({configured[1] == 1'b1}) autoConfigBaseIOPortB[3:0] <= DATA[15:12]; // IO Port B
end

8'h26: begin
if ({configured[0] == 1'b1}) shutup[0] <= 1'b1; // FastRAM
if ({configured[1] == 1'b1}) shutup[1] <= 1'b1; // IO Port A
if ({configured[2] == 1'b1}) shutup[2] <= 1'b1; // IO Port B
end

endcase
end

if (AUTOCONFIG_READ == 1'b1) begin
// AutoConfig Read sequence. Here is where we publish the RAM Size and Hardware attributes.
case (ADDRESS_LOW)
8'h00: begin
if ({configured[2:0] == 3'b000}) autoConfigData <= 4'hE; // (00) FastRAM
if ({configured[2:0] == 3'b001}) autoConfigData <= 4'hC; // (00) IO Port A
if ({configured[2:0] == 3'b011}) autoConfigData <= 4'hC; // (00) IO Port B
end

8'h01: begin
if ({configured[2:0] == 3'b000}) autoConfigData <= 4'h5; // (02) FastRAM
if ({configured[2:0] == 3'b001}) autoConfigData <= 4'h1; // (02) IO Port A
if ({configured[2:0] == 3'b011}) autoConfigData <= 4'h1; // (02) IO Port B
end

8'h02: autoConfigData <= 4'h9; // (04)

8'h03: begin
if ({configured[2:0]} == {3'b000}) autoConfigData <= 4'h8; // (06) FastRAM
if ({configured[2:0]} == {3'b001}) autoConfigData <= 4'h9; // (06) IO Port A
if ({configured[2:0]} == {3'b011}) autoConfigData <= 4'hA; // (06) IO Port B
end

8'h04: autoConfigData <= 4'h7; // (08/0A)
8'h05: autoConfigData <= 4'hF;

8'h06: autoConfigData <= 4'hF; // (0C/0E)
8'h07: autoConfigData <= 4'hF;

8'h08: autoConfigData <= 4'hF; // (10/12)
8'h09: autoConfigData <= 4'h8;
8'h0A: autoConfigData <= 4'h4; // (14/16)
8'h0B: autoConfigData <= 4'h6;

8'h0C: autoConfigData <= 4'hA; // (18/1A)
8'h0D: autoConfigData <= 4'hF;
8'h0E: autoConfigData <= 4'hB; // (1C/1E)
8'h0F: autoConfigData <= 4'hE;
8'h10: autoConfigData <= 4'hA; // (20/22)
8'h11: autoConfigData <= 4'hA;
8'h12: autoConfigData <= 4'hB; // (24/26)
8'h13: autoConfigData <= 4'h3;

default:
autoConfigData <= 4'hF;

endcase
end
end
end

// Output specific AUTOCONFIG data.
//assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ({autoConfigBaseFastRam[7:0]} == {8'h0}) && ({autoConfigBaseIOPortA[7:0]} == {8'h0}) && ({autoConfigBaseIOPortB[7:0]} == {8'h0})) ? autoConfigData : 4'bZZZZ;
assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA) ? autoConfigData : 4'bZZZZ;

// RAM Control arbitration.
assign CE_LOW = ~(FASTRAM_RANGE);
assign CE_HIGH = ~(FASTRAM_RANGE);
assign OE_LOW = ~(FASTRAM_READ && ~LDS);
assign OE_HIGH = ~(FASTRAM_READ && ~UDS);
assign WE_LOW = ~(FASTRAM_WRITE && ~LDS);
assign WE_HIGH = ~(FASTRAM_WRITE && ~UDS);

endmodule

EDIT: Stupid copy-paste removed my indents. I really need to put this in Git!

[plasmab]

Originally Posted by PR77

Here is the whole thing. Perhaps it helps with the context.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 21:28:36 11/05/2017
// Design Name: Amiga 500 in socket 68000 Accelerator, FastRAM and IDE Interface
// Module Name: A500_RAM
//
// Designer Name: Paul Raspa
//
// Revision:
// Revision 1.0
// Additional Comments:
// 07/01/2018: Maps 1MByte of FastRAM to AutoConfig location. MID 1977, PID 103
// Due to PIN Count of the VQ44 3 spare pins are available which
// could be used to map an additional 1MByte and control the extra
// /CS of the additional RAM. /OE and /WE can be /OE can be tied
// all together. THIS HAS NOT BEEN TIRED.
// 21/01/2018: Added support for two I/O spaces for Fast Ethernet and MP3.
//
//////////////////////////////////////////////////////////////////////////////////

module A500_RAM(
// Control Inputs

input RESET,
input CLK,
input RW,
input AS,
input UDS,
input LDS,

// Address Inputs
input [6:0] ADDRESS_LOW,
input [23:16] ADDRESS_HIGH,

// Data Inputs / Outputs
inout [15:12] DATA,

// RAM Control Outputs
output CE_LOW, CE_HIGH,
output OE_LOW, OE_HIGH,
output WE_LOW, WE_HIGH
);

reg [2:0] configured = 3'b000;
reg [2:0] shutup = 3'b000;
reg [3:0] autoConfigData = 4'b0000;
reg [7:0] autoConfigBaseFastRam = 8'b00000000;
reg [7:0] autoConfigBaseIOPortA = 8'b00000000;
reg [7:0] autoConfigBaseIOPortB = 8'b00000000;
reg writeStable = 1'b0;

wire AUTOCONFIG_RANGE = ({ADDRESS_HIGH[23:16]} == {8'hE8}) && ~AS && ~&shutup && ~&configured;
wire AUTOCONFIG_READ = (AUTOCONFIG_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire AUTOCONFIG_WRITE = (AUTOCONFIG_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire FASTRAM_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseFastRam[7:4]}) && ~AS && configured[0];
wire FASTRAM_READ = (FASTRAM_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire FASTRAM_WRITE = (FASTRAM_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire IOPORTA_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseIOPortA[7:4]}) && ~AS && configured[1];
wire IOPORTA_READ = (IOPORTA_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire IOPORTA_WRITE = (IOPORTA_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire IOPORTB_RANGE = ({ADDRESS_HIGH[23:20]} == {autoConfigBaseIOPortB[7:4]}) && ~AS && configured[2];
wire IOPORTB_READ = (IOPORTB_RANGE && (RW == 1'b1) && (~LDS || ~UDS));
wire IOPORTB_WRITE = (IOPORTB_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

// Generate a Write Stable signal for timing Bus Assertions after UDS || LDS are LOW.
always @(negedge CLK) begin

if (RESET == 1'b0)
writeStable <= 1'b0;
else begin

if ((AS == 1'b0) && (RW == 1'b0) && ((~LDS) || (~UDS)))
writeStable <= 1'b1;
else
writeStable <= 1'b0;
end
end

// AUTOCONFIG cycle.
always @(posedge CLK) begin

if (RESET == 1'b0) begin
configured[2:0] <= 3'b000;
shutup[2:0] <= 3'b000;
autoConfigBaseFastRam[7:0] <= 8'h0;
autoConfigBaseIOPortA[7:0] <= 8'h0;
autoConfigBaseIOPortB[7:0] <= 8'h0;
end else begin

if (AUTOCONFIG_WRITE == 1'b1) begin
// AutoConfig Write sequence. Here is where we receive from the OS the base address for the RAM.
case (ADDRESS_LOW)
8'h24: begin

if (configured[2:0] == 3'b000) begin
autoConfigBaseFastRam[7:4] <= DATA[15:12]; // FastRAM
configured[0] <= 1'b1;
end

if (configured[2:0] == 3'b001) begin
autoConfigBaseIOPortA[7:4] <= DATA[15:12]; // IO Port A
configured[1] <= 1'b1;
end

if (configured[2:0] == 3'b011) begin
autoConfigBaseIOPortB[7:4] <= DATA[15:12]; // IO Port B
configured[2] <= 1'b1;
end
end

8'h25: begin
if ({configured[2:0] == 3'b000}) autoConfigBaseFastRam[3:0] <= DATA[15:12]; // FastRAM
if ({configured[0] == 1'b1}) autoConfigBaseIOPortA[3:0] <= DATA[15:12]; // IO Port A
if ({configured[1] == 1'b1}) autoConfigBaseIOPortB[3:0] <= DATA[15:12]; // IO Port B
end

8'h26: begin
if ({configured[0] == 1'b1}) shutup[0] <= 1'b1; // FastRAM
if ({configured[1] == 1'b1}) shutup[1] <= 1'b1; // IO Port A
if ({configured[2] == 1'b1}) shutup[2] <= 1'b1; // IO Port B
end

endcase
end

if (AUTOCONFIG_READ == 1'b1) begin
// AutoConfig Read sequence. Here is where we publish the RAM Size and Hardware attributes.
case (ADDRESS_LOW)
8'h00: begin
if ({configured[2:0] == 3'b000}) autoConfigData <= 4'hE; // (00) FastRAM
if ({configured[2:0] == 3'b001}) autoConfigData <= 4'hC; // (00) IO Port A
if ({configured[2:0] == 3'b011}) autoConfigData <= 4'hC; // (00) IO Port B
end

8'h01: begin
if ({configured[2:0] == 3'b000}) autoConfigData <= 4'h5; // (02) FastRAM
if ({configured[2:0] == 3'b001}) autoConfigData <= 4'h1; // (02) IO Port A
if ({configured[2:0] == 3'b011}) autoConfigData <= 4'h1; // (02) IO Port B
end

8'h02: autoConfigData <= 4'h9; // (04)

8'h03: begin
if ({configured[2:0]} == {3'b000}) autoConfigData <= 4'h8; // (06) FastRAM
if ({configured[2:0]} == {3'b001}) autoConfigData <= 4'h9; // (06) IO Port A
if ({configured[2:0]} == {3'b011}) autoConfigData <= 4'hA; // (06) IO Port B
end

8'h04: autoConfigData <= 4'h7; // (08/0A)
8'h05: autoConfigData <= 4'hF;

8'h06: autoConfigData <= 4'hF; // (0C/0E)
8'h07: autoConfigData <= 4'hF;

8'h08: autoConfigData <= 4'hF; // (10/12)
8'h09: autoConfigData <= 4'h8;
8'h0A: autoConfigData <= 4'h4; // (14/16)
8'h0B: autoConfigData <= 4'h6;

8'h0C: autoConfigData <= 4'hA; // (18/1A)
8'h0D: autoConfigData <= 4'hF;
8'h0E: autoConfigData <= 4'hB; // (1C/1E)
8'h0F: autoConfigData <= 4'hE;
8'h10: autoConfigData <= 4'hA; // (20/22)
8'h11: autoConfigData <= 4'hA;
8'h12: autoConfigData <= 4'hB; // (24/26)
8'h13: autoConfigData <= 4'h3;

default:
autoConfigData <= 4'hF;

endcase
end
end
end

// Output specific AUTOCONFIG data.
//assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ({autoConfigBaseFastRam[7:0]} == {8'h0}) && ({autoConfigBaseIOPortA[7:0]} == {8'h0}) && ({autoConfigBaseIOPortB[7:0]} == {8'h0})) ? autoConfigData : 4'bZZZZ;
assign {DATA[15:12]} = ((AUTOCONFIG_READ == 1'b1) && ~&autoConfigBaseFastRam && ~&autoConfigBaseIOPortA) ? autoConfigData : 4'bZZZZ;

// RAM Control arbitration.
assign CE_LOW = ~(FASTRAM_RANGE);
assign CE_HIGH = ~(FASTRAM_RANGE);
assign OE_LOW = ~(FASTRAM_READ && ~LDS);
assign OE_HIGH = ~(FASTRAM_READ && ~UDS);
assign WE_LOW = ~(FASTRAM_WRITE && ~LDS);
assign WE_HIGH = ~(FASTRAM_WRITE && ~UDS);

endmodule

EDIT: Stupid copy-paste removed my indents. I really need to put this in Git!

Yeah dont use the SPI example code, the chained modules in the dev branch.

[PR77]

Originally Posted by plasmab

EDIT: If you're running out of PTerms you're doing it wrong. My code is optimized by hard hard experience for ISE.

I will look into it... To be honest I only started using ISE and verilog this year and I need to switch my embedded software thoughts into hardware. Verilog can trick you this way! At least that is my impression...

[EzdineG]

@plasmab

Can the current RC firmware handle additional Z2 RAM or is this a plan for the future? There’s a branch of MKL’s RAM68k that allows a drop to 4MB right into the 68000 socket I’d like to test.

Thanks

[plasmab]

Originally Posted by EzdineG

@plasmab

Can the current RC firmware handle additional Z2 RAM or is this a plan for the future? There’s a branch of MKL’s RAM68k that allows a drop to 4MB right into the 68000 socket I’d like to test.

Thanks

Yes. 4Mb will be ok.

Originally Posted by PR77

I will look into it... To be honest I only started using ISE and verilog this year and I need to switch my embedded software thoughts into hardware. Verilog can trick you this way! At least that is my impression...

Verilog defines flip flops and combinatoric logic. Nothing else. Its not a programming language with flow. The sensitivity list on a block defines the pins to the CLK, SET, CLR lines and the code inside begin end tags defines CLK Enable, and D. thats it.