25 November 2018, 16:52 | #881 | ||||||||||||||||||||
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After all, creating a CPU that can't be reliably coupled with the available support hardware of the time (in this case due to running at too high a bus speed to work properly) isn't a sign of doing the job of designing a CPU particularly well. You might disagree, but apparently this is how the market viewed it, as seen here: Quote:
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I can't find it now, but during my Googling on this bug and it's impact I did run into people talking about needing to work around it. Quote:
I'll give one example (there are many, many more), look at the popular 3D rendering program Imagine. This always came in both FPU enabled and non-FPU versions included. You could even check which version you were running. See a screenshot of what I mean here: http://obligement.free.fr/articles/imagine50.php Now, I am only talking about 68k based software here. I have no clue how x86 software dealt with this. Maybe on x86 FPU emulators were more frequent, but on 68k they were very rare. I used Amiga's for years back then and didn't even know these things existed. Quote:
I'll agree that this isn't a common thing to do, but it is 100% possible. Quote:
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Also, note that I'm not saying it never was a problem, just that it only rarely was one - even for software that would benefit from a FPU. And again, for those few affected - Motorola would exchange the CPU for free. Quote:
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2) Your evidence for the ISA being the problem here is based solely on your opinion. A far more likely reason for Motorola running out of transistors can probably be found in the speed difference of the stuff that was kept in - as we've discussed, the 68040 is faster than the 486 at the same clock speed. And the primary way to make a CPU do the same things as before, but faster, is to throw more transistors at the problem (this is a very widely known fact and allows us to explain the differences we see without relying on flawed opinions). Quote:
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Oh and it got said upgrade by implementing a new model that was incompatible with the 8086. This stupidity had resulted in every single x86/x64 CPU ever released still starting up like it's 1978 and then having to switch to something that is actually useful. Quote:
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Note that virtual 8086 mode is a form of hardware emulation that requires the OS to have a special '8086 handler'. Without the handler 8086 code wouldn't work. The very nature of virtual real mode prove my point: the processor needs to emulate an 8086 in order to be able to execute real mode code. And again: if this 'virtual real mode' is not used, 8086 code will crash the machine. Quote:
This is extremely widely known and I really don't understand why you keep repeating clearly false information. Here then some quotes from the protected mode wiki to show what I mean: Quote:
By the way, benchmarks would be very interesting (do you have these results somewhere?), but note that even as you claim there is no difference, you also claim that IO is half speed - which is a speed difference. Quote:
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Last edited by roondar; 26 November 2018 at 10:55. |
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26 November 2018, 02:24 | #882 | |||
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Intel and the x86 Architecture: A Legal Perspective Quote:
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26 November 2018, 08:44 | #883 |
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68k is still alive in the embedded world: https://www.nxp.com/products/process...ldfire:PC68KCF
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26 November 2018, 11:12 | #884 | ||||||||
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Motorola felt that it alone could not compete with Intel because Intel had so many more resources than Motorola due to the success of the IBM-compatible PC. Hence, they were looking for alliances and teamed up with IBM. They probably thought that teaming up with IBM who were at the root of Intel's success due to the choice of the Intel CPU for the "IBM-compatible" was a good idea. And there was no better option. IBM has also been very popular for alliances in the semiconductor fabrication department. There it is just the same: Intel vs IBM et al. Interestingly at the time the PowerPC was introduced it was said and believed that the PowerPC was a CPU very good at emulating other CPU architectures. It was even believed that due to the PowerPC being RISC it would soon be able to emulate not only 68k (that was assumed to be a given) but also x86 faster than the original chips ran. So you could argue that the PowerPC was designed with a "universal compatibility mode" in mind. Quote:
You may find it interesting that the Apollo Team's 68080 core used in the Vampire accelerator cards is in its core a RISC-CPU having a three-operand ALU and running 68k code. It is more or less using the implementation ideas of the PentiumPro to Pentium III CPUs with some even more modern additions. If Motorola had decided to stick with the 68k ISA, they could just as well have designed a 68k CPU using the same tricks as Intel. There is nothing "too heavy" about the 68k ISA to be implemented on top of a RISC core. Quote:
Moreover, if you think that dividing the register file into data and address registers doesn't make sense, then please consider that in today's processors peak loads are handled in 128bit and 256bit registers (everything SSE and all those cryptographic execution units have much wider registers than 32 or 64 bits) effectively introducing another arbitrary separation in the register file. Quote:
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Not executing them in hardware (where they are microcoded anyway) has some advantages, most notably the ability to select precision of the operation and running integer code in parallel. Quote:
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26 November 2018, 11:50 | #885 | |
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It feels like a fairly logical progression to me, anyway. |
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26 November 2018, 12:05 | #886 |
son of 68k
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Actually the D/A split is a very clever idea, it basically allows having 16 registers with the cost of 8.
Imagine what the encoding would be with a 4-bit register field instead of a 3-bit one. You have either to make instructions larger, killing the code density completely, or to severely trim the instruction set, or a combination of both. In either case, it's not nice. But of course many programmers don't know how instructions are encoded and they see that only as an annoyance. They forget that other families with 16 registers either use large code words (like arm) or ugly prefixes (like x86), while on the 68k a small 16-bit opcode can access them all and still provide a great instruction set. |
26 November 2018, 13:11 | #887 | |
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The same could be said about 2-operand vs. 3-operand code and yet everybody uses (at least) three operands today. With 3-operand code, one bit for implying A or D registers and a (very useful) S-flag you'd be left with just 5 bits for encoding instructions which would have to be enough to also encode CISC address modes with e.g. a source/destination flag and some ea-type flag. At this point it is evident that you either stick with 2-operand code if you really want to keep 16 bit instruction words or use 32 bit instruction words. But anyway, let's not turn this into a debate about how an ideal ISA should look like, we have had enough of those. Let me stress again that I do agree that separate A and D registers have some important advantages over GPRs. Personally I like GPRs better than a fixed split between A and D type registers because I find the flexibility of e.g. using 12 registers for data and three for addresses more important. I have been in need of more than eight D registers many times and hardly ever needed seven A registers in speed critical code. |
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01 December 2018, 11:47 | #888 | ||||||||||||||||||
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I have added to the article the next text:
The oddities with flags do not finish at this. For some unknown reason, many commands, including even MOVE, null the flags of carry (C) and overflow. Another oddity is that the command to save the state of arithmetic flags, which worked normally at 68000, was made privileged in all processors starting at 68010. Interestingly, IBM simultaneously with the development of the PC led the development of the System 9000 computer based on the 68000, which was released less than a year after the PC. So IBM worked with 68k but it was too expensive for a mass computer until 1984. Apple Lisa proved this too. A man sent several more messages to meynaf - https://litwr.livejournal.com/2509.h...ead=4813#t4813 - maybe it will be worth to remove his ban? Quote:
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movsw lodsw mov [ebx],ax add 2,ebx lodsw mov [ecx],ax add 2,ecx lodsw mov [edx],ax add 2,edx Quote:
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It is interesting when Motorola started to have second sources? Was it 1979 or much later? Quote:
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01 December 2018, 13:53 | #889 | ||||||||
son of 68k
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Check what MOVE+BLE (or BGT) combination could do if MOVE didn't clear V. Quote:
On 68010 was created MOVE CCR for the arithmetic flags. This was to fix a design bug ! The issue is this : allowing to read the whole SR makes virtualization more tricky, if not impossible. A sandbox needs the sandboxed program to "believe" it is actually the supervisor, when in reality it is not. So it will run in user mode and the sandbox will "emulate" all his supervisor stuff. Now let's consider what happens if the hosted program saves SR for whatever reason, then restores it. It will save SR with S=0 (user mode) because the sandbox can't catch it, then restore it with S=0 (user mode again). The sandbox will then consider it wants to return to user mode... which wasn't the case. Result : crash'n'burn. On the other hand, if MOVE SR is privileged, the sandbox will emulate the call and return a correct value with S=1. I don't know if my explanation is clear. Do you see the problem ? So, ok, it's true the average Amiga user does not need that. But workstations might. Quote:
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Thanks for pointing me to his replies, btw. I hope we can discuss in a more friendly manner in the future, even if we clearly don't agree. Quote:
You say some instructions can't be used there, but i don't see any. So, examples please. Quote:
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(And many more than 8 bytes). Now consider a c2p : 1 source, 8 dest, 8 data, 1 loop counter... It does not make it less dirty. Some Atari ST programs do exactly the same, and they're a pain to get ported. |
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01 December 2018, 18:32 | #890 | ||||||||||
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The real reason they're rare is that, on average, most software didn't actually need an FPU back in those days. This goes for both x86 systems and 68k systems. I knew quite a few people with a PC and no-one had a 8087/80287. One or two did have a 80387 later on, but only because it came with the system - they didn't actually need one either. You're simply vastly overstating the usefulness of an FPU in the 1980's and early 1990's to the average user. An 8087 coprocessor box from Intel from 1987 (or later) pointed to all of 160 programs that could benefit. Wow, what a large number out of the thousands and thousands of programs out there at the time. It sure sounds like a must have accessory https://www.worthpoint.com/worthoped...sor-1856611681 Quote:
Your arithmetic example even proves my point - if you check the cycle times of the 16 bit add/sub commands for both you will quickly find that the 65816 isn't always faster even clock for clock (i.e. the 65816 actually is slower clock for clock than the 68000 on some of these commands) and when it actually is faster clock for clock, it still is never over 2x as fast so it'll at best be the same speed when compared to a 68000@8MHz - even on instructions you yourself present here as being faster. And that leaves out the main problem that the 6502/65816 faces, which is that the Motorola tends to simply need less instructions to do the same things as a 6502/65816 by virtue of not being an accumulator based design - even if we pretend that multiply and divide don't exist. This difference is somewhat smaller with 68000 vs 65816 as the 65816 adds a bunch of instructions, but still very clearly exists. Which means that looking at instruction cycle counts of simple stuff only tells a small part of the story. And a wrong one at that. The blockmove is nice though, I'll grant you that. Now, I've not been able to find other 65816 benchmarks, other than a few references to them on the 6502.org website (where apparently the 65816 lost to the 68000 on the sieve benchmark by a rather significant margin, though they did not provide a link). Interestingly, people on that forum concluded that the 65816 would indeed be faster than the 68000 - if they both ran at the same clock. And I'd agree with that. Of course, it would still lose at half the clock speed - given the few data points we do have and the fact that the very fans of the CPU didn't claim it themselves (if I was a 6502 fan I would certainly claim such a thing if it were true!). Could there be benchmarks in which the 65816 wins? Well, show them and I'll admit defeat. But claiming something when the only evidence says you are wrong is clearly not going to work. Quote:
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The point here then, isn't that these functions couldn't be useful, but rather than they (for whatever reason) were used only rarely. That you personally don't understand why this was so is honestly completely irrelevant - it won't change the facts. Quote:
Would it have been nicer to have these functions? Sure. But not by as much as you think and the cost to keep them was apparently too great. Quote:
The 8088 was not a 'middle class' computer by the end of the 1980's, it may have delivered mid-range performance in 1979, but was completely obsolete by 1985. The Apple's, Atari's, Amiga's, PC-AT's out by then absolutely trounced it performance wise. As for 80286/80386/etc - that is completely irrelevant. This part of our discussion was purely about the 8086 as designed. You've repeatedly claimed the 8086 itself (not the follow-ups, the actual 8086 CPU) was fine until the late 1980's. Yet in 1982 the design was already so far out of date that Intel redesigned it really rather thoroughly in an effort to get it up to date. But don't just take my word for it - there's this litwr guy who only a post ago said something rather similar in different words "Indeed 8086 needed a major upgrade in 1982 and it got it!". But now this other guy (I believe he's called litwr), disagrees with litwr Seriously, one post back you agree with me that the changes to the 8086 were needed and now you're straight back to claiming there was nothing wrong with it Quote:
So, just to (hopefully) break through this continued nonsense about real mode being compatible with protected mode one last time, here are the facts. Not opinions, not oddities, just facts. 1) Installing and running DOS on a modern PC proves nothing about real mode code running in protected mode, because.. DOS, even on the very latest x64 processors, does not run in protected mode. 2) Real mode code will not run in protected mode as-is. It will crash. 2) The workaround to this, namely Virtual 8086 mode, needs the OS to handle things or the real mode program will again crash. 3) The above shows that real mode code is not compatible with protected mode - if it were compatible, no workaround would ever be needed. And again, I'm not saying you can't run the CPU in real mode - you can. I'm also not saying the compatibility hacks required for Virtual 8086 mode don't work - they do. However, neither are relevant - An Intel CPU in protected mode cannot run 8086 code without requiring workaround in software. This fact proves the two modes are not compatible - no matter how often you make claims about running DOS or using an OS that has these workarounds built-in. After all, if the OS using workarounds is an acceptable solution then your original point (remember were we started this) about some 68k code not being compatible with 68010+ is null and void - you can simply have the OS reset the VBR and run any offending program in supervisor mode. This is much less work than virtual 8086 mode requires and works just fine. Quote:
Oh and I found a lovely gem on the Wikipedia page on the PDP-11: Quote:
Last edited by roondar; 01 December 2018 at 19:07. |
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01 December 2018, 20:00 | #891 | |
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lodsw mov [off1+di],ax lodsw mov [off2+di],ax lodsw mov [off3+di],ax movsw add di,6 |
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01 December 2018, 20:41 | #892 | ||
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And you don't think in 68k way yet. Else you wouldn't write the same things Quote:
Yes but it also "allows" using memory without a prior allocation. |
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01 December 2018, 20:57 | #893 | |
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You have written Now let's consider what happens if the hosted program saves SR for whatever reason, then restores it. We are speaking only about reading! Indeed the restoration of SR should be privileged and it was privileged. PIC. Sorry I again should repeat the same thing. When you write a COM-program you don't need to be aware of anything but size of the segments - you get PIC automatically. BTW I have some experience of work with experimental high-performance hardware based on Xilinx Microblaze variant without MMU. People wanted to run Minix with it so they just added two segment registers (for code and data) into hardware and using them they got PIC for every Minix program. Minix works with this system with this cheap and easy trick. It was possible to run even Linux this way but Linux uses MMU too often and this trick will often slow down performance too much. For 68k you should write your code in a special way. Without C-sources it will be almost impossible to organize a contest. |
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01 December 2018, 21:49 | #894 | |||||||
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LOL. Of course, Intel stole the idea of LE byte order from DEC! It is a real Wikipedia's gem. I can estimate that 68k design is about 60-70% from DEC but Intel less than 10%. |
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01 December 2018, 23:57 | #895 | |
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All the FP primitives are much much faster. Something like 4x on the 040 at the same clock. I have an 040 based Amiga btw. 40 mhz 040 blizzard. They weren't rare. |
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02 December 2018, 00:06 | #896 | |||||||
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There was virtually no software available that made use of an FPU as Intel's own marketing shows*. Them selling a bunch of them anyway is more of a sign of customer stupidity and/or clever marketing than usefulness of the product.
*) Not just Intel's marketing by the way. It's common knowledge that computers in the 1980's and 1990's tended to shy away from floating point math for all but the most esoteric of cases (such as 3D rendering). Even the 'Amiga killer' Doom just ran plain old integer code. Quote:
http://www.skepticfiles.org/cowtext/...1/486vs040.htm on the linpack FP benchmark: "Here, the MC68040 outperforms the 80486 by a factor of 3. This performance ratio is well supported by the discussion given for the data in Table 1.1." Now this is only one data point and it may well be too positive, but that one data point is still much, much more than you've offered as evidence for your claims, which is zero. Quote:
It was a compromise. It worked and didn't 'mutilate' anything other than a few fractal rendering programs. Just like the lowering of front bus speed by Intel later on was a necessary compromise that worked 'for about a year'. Besides, removing rarely used instructions or features to make room for more instructions or better performance is a much better idea than keeping everything in at all costs - just ask Intel how it's push for mobile dominance is going and then ask the same of ARM to see why (as ARM actually does, from time to time, remove instructions from it's instruction set. Amusingly, they use similar kinds of logic to that used by Motorola during the 68040 design - instructions that don't offer enough 'bang for the silicon' get removed) https://stackoverflow.com/questions/...rm-instruction Quote:
FYI: the only reason the Atari & Amiga 500 did well in the market is precisely because they were low end and thus rather cheap (unlike your example, which would've been shockingly expensive for the pitiful CPU power it gave you), but were still very good for one key workload: gaming. Which your example machine would be very poor at indeed as EGA is no good without at least a fast 286. And seriously, office work? In those days that screamed 'any old underpowered, obsolete hardware will do'. No one in their right mind sees office PC's in the 1980's as anything other than crap Quote:
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As just one of many examples, there is T.U.D.E. (The Ultimate Degrader and Enhancer) which allows you to run programs with a number of options for compatibility. Amongst other things, T.U.D.E. lets you run software that would fail on 68010+ due to privilege errors (Fixing the move from SR problem), allows you to kill the cache (fixing self modifying code), reset the MMU (if any), reset the VBR, etc. Most games work when you use this. The few that remain either fail due to requiring Kickstart 1.3 (which is also an option to use in T.U.D.E.), due to timing problems (i.e. not properly waiting on the Blitter) or the coder reading the Motorola manual and thinking "screw that, I'm going to put data in the high byte of my address registers anyway". For more proof the problem (on Amiga) is almost never the processor, note that WHDLoad slaves almost always have to fix Blitter coding and less frequently kill caches or enable supervisor flags for incompatible programs. They almost never need to touch the actual program code (apart from Blitter coding as mentioned or if the program was buggy on 68000 also). Quote:
A Pentium/x86/x64 based version of this type of device still won't work even today because Intel just can't seem to manage making an x86 CPU that is even semi-worthwile if it can't use all the power in the world Quote:
Last edited by roondar; 02 December 2018 at 12:58. |
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02 December 2018, 11:14 | #897 | ||||||
son of 68k
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But MOVE setting the flags is very, very useful. Quote:
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If the read gives a wrong result, then restoring also will. Hence both must be privileged. Quote:
You can get PIC on 68k if you setup the assembler to produce it (setup small data model). So you can get it automatically as well. But you can get it for larger programs than just 64k. On the other hand, having to take care about the size of the data segments is a lot more intellectual load than just using relative addressing modes. Quote:
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Anyway, if it's necessary for you, why don't you find one then ? |
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07 December 2018, 21:21 | #898 |
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@meynaf
Code:
lodsw mov [off1+di],ax lodsw mov [off2+di],ax lodsw mov [off3+di],ax movsw Code:
move.w (a0)+,(a1)+ move.w (a0)+,(a2)+ move.w (a0)+,(a3)+ move.w (a0)+,(a4)+ @roondar 8-bit data bus at 65816 slows down this CPU very much. My point was that a 65816 variant with 16-bit data bus @4MHz should be faster than 68000 @8MHz. Last edited by litwr; 08 December 2018 at 10:36. |
08 December 2018, 03:56 | #899 | |
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But that's silly anyway. The instructions are meant to be executed over and over again in a loop so that 7 instructions vs 5 makes a difference. |
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08 December 2018, 10:43 | #900 | |||
son of 68k
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Learn how to count. This is 4 instructions, not 5 So you added one ghostly instruction to use 10 > 9. Was it intentional ? Quote:
Not only it would be 9, not 10 because 4 isn't equal to 5, but in addition you forget that on 68k we have something very powerful that's just missing in x86. So to load registers we can simply do : Code:
movem.l planes,a1-a4 9 > 7 and thus x86 has more instructions for the case. Note that even your point about the necessity to load 4 registers is wrong, as in 68k we could do : Code:
move.w (a0)+,(a1)+ move.w (a0)+,off1-2(a1) move.w (a0)+,off2-2(a1) move.w (a0)+,off3-2(a1) |
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