Instruction cache question

[Lord Riton]

Hello,

How much time does the 68030 lose on a instruction cache miss ?

I suppose because he has 16 byte cache entrys he will always fill 16 bytes at least, so does this mean i only get a cache miss , then 7 instructions on cache, then a cash miss then 7 on cash and so on (in case of the instructions beeing sequential and taking 2 bytes each) ?

[Kalms]

More or less correct, if burst mode is enabled for the instruction cache. And normally it should be.

You can expect each stall to last for about 10-15 cycles on your 030@28 board.

The general strategy for 68020/68030 is, "make sure that your innermost loop is <240 bytes in size", because then you don't need to worry about alignment and stuff. If your innermost loop spills out of the cache then those icache reads will most likely eat up any time you saved by unrolling loops.

[Lord Riton]

Originally Posted by Kalms

More or less correct, if burst mode is enabled for the instruction cache. And normally it should be.

You can expect each stall to last for about 10-15 cycles on your 030@28 board.

The general strategy for 68020/68030 is, "make sure that your innermost loop is <240 bytes in size", because then you don't need to worry about alignment and stuff. If your innermost loop spills out of the cache then those icache reads will most likely eat up any time you saved by unrolling loops.

I see thanks for the info

It's how i guessed it. I made a new c2p code, but it's long, and way longer than 240 bytes. If i add my new c2p code to QON it would only improve rendering on a 040 or 060, because it's main loop is taking arround 1kb.
Guess i'll just abandon the newer routine, i don't want to make improvements only for these processor based Amigas.