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Old 08 May 2010, 00:03   #21
Shadowfire
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Reread first post. It is a 2-board set.

Signals are transmitted from the DE2 via 80-conductor cables with every other wire grounded, to reduce crosstalk. This allows you to place the DE1 on the table beside the unit you are attaching it to. I haven't done calculations but at 8mhz you should be able to easily use 3' of cable without any significant signal degradation or crosstalk (reflections will be reduced by the quickswitches and existing slew rate damping resistors on the DE1, but I plan on allowing you to add more series resistance on the 40->80 converter board if needed).

There is no compensation for signal skew, but at the frequencies that the 68000 operates, a few inches difference shouldn't matter that much. Just got to be careful with your I/O interface timing. But then, you always have to be careful with your I/O timing.

Last edited by Shadowfire; 08 May 2010 at 00:12.
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Old 08 May 2010, 04:22   #22
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Quote:
Originally Posted by Shadowfire View Post
Reread first post. It is a 2-board set.

Signals are transmitted from the DE2 via 80-conductor cables with every other wire grounded, to reduce crosstalk. This allows you to place the DE1 on the table beside the unit you are attaching it to. I haven't done calculations but at 8mhz you should be able to easily use 3' of cable without any significant signal degradation or crosstalk (reflections will be reduced by the quickswitches and existing slew rate damping resistors on the DE1, but I plan on allowing you to add more series resistance on the 40->80 converter board if needed).

There is no compensation for signal skew, but at the frequencies that the 68000 operates, a few inches difference shouldn't matter that much. Just got to be careful with your I/O interface timing. But then, you always have to be careful with your I/O timing.
I have used a similar approach at work with a 50 pin IDC cable : 25 signals and 25 grounds. The clock speed was around 8 - 10 MHz. I had to put termination resistors of 100 - 120 ohm at the connector to not have "staircase" waveforms.
The impedance of an IDC cable with alternating signal / ground is 120 ohms.
All my signals were one way, with bidir signals, it is trickier.

Regards,

Frederic
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Old 10 May 2010, 23:36   #23
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I'm using .025" ribbon cable, which should have a characteristic impedance of 75 - 80 ohms. Altera already put 47 ohm terminators in, I'm going to have a look with my scope once the boards are done to see how bad it is (and if I need to put more on it). Thinking of going with the Vishay VSSR resistor networks for this, they worked pretty good before, and should be small enough for the board.
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Old 14 May 2010, 03:21   #24
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Oh my, I almost made boards for a connector that everyone wants a minimum order of 750 units on. Eep! Going to have to hunt down cheaper and more available connectors.
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Old 15 May 2010, 17:38   #25
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Oh my, I almost made boards for a connector that everyone wants a minimum order of 750 units on. Eep! Going to have to hunt down cheaper and more available connectors.
Why not using just two 40-wire IDE cable (we cannot use 80-wire cable because of the wrong locations of the GND pins) ?
Then, you stick around the cable some duct tape that you connect to the ground. We can solve a lot of issue with duct tape, right ?

Regards,

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Old 16 May 2010, 10:42   #26
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Crosstalk? Signal integrity? I don't want to have to ask, "Why is this flaking out sporadically?"

Actually, I found some far more affordable 80 pin headers & IDC cable connectors from Sullins (SBH41-NBPB-D40-SM-BK headers, and SFH413-PPPB-D40-ID-BK cable connectors), they are only $3 each. As a bonus the headers are cheaper than the Samtec strips I originally called for. I think I've finalized the voltage board and I'm trying to transfer the design to expresspcb's board software, but it will be challenging (read: time consuming) as there is no autorouter, and the manual router is very, very, primitive (yes, there isn't even a ratsnest option. Think about it.).

This would allow me to get the cheap proto board rates from them. Otherwise I need to ship it off to one of the typical proto houses, which is going to cost $180-ish for 2 boards (versus $100 for 3 boards from expresspcb). The layout is final on the voltage board though.
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Old 17 May 2010, 00:58   #27
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I think I am gonna give a try to a slightly different board.
I am putting the 68000 and 6510 footprint on it and directly connect the 40-pin IDC cables on it, with some duct tape .
BTW, Tobias has done an Amiga accelerator using a DE2 board and just some flat cable connection to the A500.

Regards,

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Old 28 May 2010, 15:40   #28
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Any more information (or a link perhaps) for this "accelerator"?
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Old 29 May 2010, 00:11   #29
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No such product exists.
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Old 03 June 2010, 13:20   #30
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Well I doubt FrenchShark made it up..
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Old 08 June 2010, 00:15   #31
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Recent progress...


Last edited by Shadowfire; 08 June 2010 at 00:27.
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Old 08 June 2010, 00:20   #32
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@Glenn: the picture does not exists.
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Old 08 June 2010, 00:27   #33
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fixed, my bad.
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Old 08 June 2010, 05:01   #34
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Looking good.

But may I ask something a bit unusual? Use ordinary sockets for the 68000.

From my experience the rounded pin ones are a bitch to insert the CPU back into, and also may have bad contact.
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Old 09 June 2010, 03:58   #35
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Nothing stopping you from installing your own preferred socket in J3, although you may need to cut out the socket's interior crossbars if they interfere with the quickswitches.

The IBoard came yesterday. Today I populated it, rang it out, and fixed any shorts/no connects.



I hooked it up as intended (although I didn't power it up - I still need to do a final check of the entire unit for shorts & opens, after I get the last resistor I need [a surface mount 0603 45ohm resistor, which should be arriving on Friday] and took a picture of the fixture & DE1. The cables are about 2.5 feet long.



I still need to do some VHDL coding (68000 socket slave to wishbone, then a wishbone SRAM slave) to confirm everything is working and check signal integrity with my oscilloscope. Assuming everything checks out OK, I will post schematics & gerbers on my blog. There is 1 spare VBoard and 2 spare IBoards.

As usual, my price estimation abilities were terrible.

$180 - Two Vboard prototype boards
$150 - Three Iboard prototype boards
$220 - Vboard IC's, sockets, passives, connectors, and cabling for 1 complete unit

Last edited by Shadowfire; 09 June 2010 at 04:11.
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Old 12 June 2010, 01:05   #36
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A few minor updates:

All shorts/opens seem to have been addressed, end-to-end, on the entire system.

VCC4.3 was putting out 4.5V instead of the expected 4.3V. Some probing led to the Zener feeding the opamp 4.5V instead of 4.3V. A trip to the datasheet revealed my mistake; I had biased the zener for ~10mA, when the datasheet shows a zener current of 5mA. Correcting the biasing resistor (using a pair of series 75ohm resistors, a little higher than the 140ohms I calculated) resulted in a zener voltage of ~4.27V, and 5.00V signals being clipped at 3.35V.

At this point the hardware is pretty much set in stone, the only thing that may change is the terminating resistors, once I get the VHDL up and running. This will probably be my last post on this for a while.
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Old 03 July 2010, 16:41   #37
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::grumbles:: External PLL needed to multiply 7.14Mhz system clock, since the Cyclone's internal PLL's can't be used at input frequencies < 10Mhz.
As it is, synchronizers from the wishbone -> 68000 bus result in 3 wait states on a read or write.

Last edited by Shadowfire; 03 July 2010 at 17:18.
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Old 04 July 2010, 06:45   #38
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Hi Shadowfire,
Quote:
Originally Posted by Shadowfire View Post
::grumbles:: External PLL needed to multiply 7.14Mhz system clock, since the Cyclone's internal PLL's can't be used at input frequencies < 10Mhz.
As it is, synchronizers from the wishbone -> 68000 bus result in 3 wait states on a read or write.
How about a flying lead off the 68K socket board to the 28MHz source in the Amiga?
Or are all the signal lines back to the GPIO sockets already in use?

Cheers,
Red
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Old 04 July 2010, 20:08   #39
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Uploaded with ImageShack.us

This is the 28mhz clock coming from the resonator (yellow), and the 7.14mhz system clock (cyan). I have edited the pic to show what the Cyclone 2 would see (VIL= 0.7V, VIH = 1.7V), with the red and blue wave superimposed.

You can clearly see, even with the limited resolution here, that the 7M clock is skewed (later than) the 28mhz clock. There is nothing I can do about what voltages the Cyclone 2 uses for its threshold. There is a lot of variance in the skew, too, just in the few cycles sampled here. Since everything on the 68000 interface is timed off of the 7M clock (which closely follows the blue wave, the 68000 has VIL=0.8V and VIH=2.0V), basing my I/O setup and hold timings on the 28mhz clock would be... lucky if it worked at all, with this much skew.

Basically, I need a 28M clock that's sync'ed to the 7M clock... and I need one of the Cyclone's internal PLL's to do that. I'm hoiping to be able to use a fast external IC to XOR the 7M and CDAC lines, and run the resulting 14 Mhz signal (which should be sync'ed exactly with a slight XOR delay) into the DE1's clock input port, and account for the minor but consistent XOR delay with my fitting constraints.

Last edited by Shadowfire; 04 July 2010 at 20:21.
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Old 05 July 2010, 13:08   #40
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Hi Shadowfire,
Quote:
Originally Posted by Shadowfire View Post

Uploaded with ImageShack.us

This is the 28mhz clock coming from the resonator (yellow), and the 7.14mhz system clock (cyan). I have edited the pic to show what the Cyclone 2 would see (VIL= 0.7V, VIH = 1.7V), with the red and blue wave superimposed.

You can clearly see, even with the limited resolution here, that the 7M clock is skewed (later than) the 28mhz clock. There is nothing I can do about what voltages the Cyclone 2 uses for its threshold. There is a lot of variance in the skew, too, just in the few cycles sampled here. Since everything on the 68000 interface is timed off of the 7M clock (which closely follows the blue wave, the 68000 has VIL=0.8V and VIH=2.0V), basing my I/O setup and hold timings on the 28mhz clock would be... lucky if it worked at all, with this much skew.

Basically, I need a 28M clock that's sync'ed to the 7M clock... and I need one of the Cyclone's internal PLL's to do that. I'm hoiping to be able to use a fast external IC to XOR the 7M and CDAC lines, and run the resulting 14 Mhz signal (which should be sync'ed exactly with a slight XOR delay) into the DE1's clock input port, and account for the minor but consistent XOR delay with my fitting constraints.
Is that 28MHz signal measured at TP1 (page F9 of the A500 manual), or just straight off the oscillator?
I would have expected the 74F04 (U33) to sharpen the signal up a bit.

Cheers,
Red
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