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Old 11 September 2011, 10:12   #61
Shadowfire
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From the Cyclone 2 Device Handbook, page 10-2

Quote:
3.3-V LVCMOS (EIA/JEDEC Standard JESD8-B)
The 3.3-V LVCMOS I/O standard is a general-purpose, single-ended
standard used for 3.3-V applications. The LVCMOS standard defines the
DC interface parameters for digital circuits operating from a 3.0- or 3.3-V
power supply and driving or being driven by LVCMOS-compatible
devices.
The LVCMOS standard specifies the same input voltage requirements as
LVTTL (– 0.3 V ≤VI ≤3.9 V). The output buffer drives to the rail to meet the
minimum high-level output voltage requirements. The 3.3-V I/O
standard does not require input reference voltages or board terminations.
Cyclone II devices support both input and output levels specified by the
3.3-V LVCMOS I/O standard.
From the Cyclone 2 Device Handbook, page 5-1, table 5-1:
Quote:
IOUT DC output current, per pin (-25 mA minimum) (40 mA maximum)
I quoted the current supply spec since you had concerns about a 2.5mA load on each line, although to be honest I wouldnt think the load of 7-8 1988 eras CMOS devices shouldnt be anywhere near that much. Where did you get the 2.5mA number from?

From table 5-6
Quote:
3.3-V LVTTL and LVCMOS (0.8V Vil MAX) (1.7V Vih MIN)
From table 5-7
Quote:
3.3-V LVTTL (0.45V Vol MAX) (2.4V Voh MIN)
The 68000 and Amgia custom chips are all based on 5V CMOS processes. There is no electrical data available on the Amiga custom chips, however in the Commodore documentation for 68040 accelerator board development, they state that the custom chips will accept the 68040's 3.3V level without a problem. Standard CMOS threshold is 2.5V for low/high decisions.

From the 68000 User's Manual, page 10-7, table 10.6:
Quote:
Characteristic Symbol Min Max Unit
Input High Voltage VIH 2.0 VCC V
Input Low Voltage VIL GND-0.3 0.8 V

Output Low Voltage VOL 0 0.5
Output High Voltage VOH VCC-.75 VCC
So, they cyclone will output 0-.45V for a low signal.
The 68000 will recognise 0-0.8V as a low signal.
The Cyclone will output 2.4 - 3.3V for a high signal.
The 68000 will recognise 2.0 - 5.0V as a high signal.

Doesnt seem to be a problem with cyclone -> 68000 signal levels to me.

The 68000 will output 0 - .5V for a low signal.
The Cyclone will recognise 0 - .8V for a low signal.

The 68000 will output 4.25V - 5V for a high signal. This will be clipped by the quickswitches to 3.3V +/- 100mV.
The Cyclone will recognise 2.4V - 4.0V as a high signal

There doesn't seem to be a problem with 68000 -> cyclone signal levels here, either, once the quickswitch is added to the circuit.

The Cyclone I/O's support bidirectional transfers as well as high-Z modes. No extra hardware logic (beyond the quickswitches) is needed to interface with the 68000's bus. Am I missing something? Why are you quoting the LVTTL spec? You are driving a CMOS circuit, you would want to use the CMOS driver voltage levels... If you are arguing that a 2.5V I/O standard on the Cyclone would be impossible, well, that's another story entirely and you'd be right, but this chip has 3.3V I/O.

Last edited by Shadowfire; 11 September 2011 at 10:18.
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Old 11 September 2011, 11:49   #62
RedskullDC
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Quote:
Originally Posted by majsta View Post
No No No this design can't work...
Check the photos section of the minimigtg68 group:

http://gamesource.groups.yahoo.com/group/minimigtg68/

The are pics of Tobiflex's DE2 board *directly driving* an A500 via the 86-pin expansion bus.
(DE2 board has diode clamping/resistors to protect the GPIO pins from 5V signals, and doesn't require any external circuitry.)

This shows the cyclone II FPGA set to LVTTL outputs driving TTL inputs.

Shadowfire's design looks quite sound to me.

Red
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Old 11 September 2011, 11:53   #63
coze
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shadowfire any developments since last version ?
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Old 14 September 2011, 03:54   #64
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Red,

The 5V levels on the I/O lines are hammering his cyclone chip I/O drivers to pieces. If he is still using that thing, I'll bet good money the FPGA is toast by now. If he has the diodes enabled, its hammering the I/O's of every 5 volt driver thats driving the I/O lines. There is supposed to be series resistors to limit current when you use the diodes like that, which affect signal rise/fall times. Also, there should be external diodes unless you can guarantee that the Cyclone will be up and running before stuff starts driving 5V onto the I/O lines (highly unlikely in this case).
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Old 14 September 2011, 05:10   #65
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Quote:
Originally Posted by Shadowfire View Post
... To tell you the truth, the whole FPGA/ASIC thing is new to me, I've been hitting books to learn this stuff, I'm primarily a software kind of guy.
I mostly write software too and have an interest in looking into hardware side of things. Just wondering which books did you find the most useful to get into hardware? Thanks.
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Old 14 September 2011, 12:01   #66
RedskullDC
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Hi Shadowfire,
Quote:
Originally Posted by Shadowfire View Post
Red,

The 5V levels on the I/O lines are hammering his cyclone chip I/O drivers to pieces. If he is still using that thing, I'll bet good money the FPGA is toast by now. If he has the diodes enabled, its hammering the I/O's of every 5 volt driver thats driving the I/O lines. There is supposed to be series resistors to limit current when you use the diodes like that, which affect signal rise/fall times. Also, there should be external diodes unless you can guarantee that the Cyclone will be up and running before stuff starts driving 5V onto the I/O lines (highly unlikely in this case).
If you look closely at the pics, Tobiflex is using a DE2 board to drive the A500 Expansion connector.

Unlike the DE1 (which has no protection), the DE2/DE2_70/DE2_115 boards have 47ohm series resistors on all the GPIO lines, plus a BAT54 diode pair clamping to +3.3 and GND respectively on the FPGA side of the resistor.
(Snippet from the DE2 shematic attached).

The external circuit employed on these boards is equivalent to the external resistor in combination with the PCI clamp diode arrangement detailed in Section 10 of the Cyclone II manual.

Perfectly safe to apply 5v to signals on the GPIO pins on these boards even during config.

Naturally, no IO standards < 3.3v should be used when talking to 5V signals. Likewise, the PCI clamp diode options should not be enabled in any projects on these boards

Cheers,
Red
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Old 12 April 2012, 21:44   #67
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Will this adapter ever be for sale? I'd love to buy one.
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Old 13 April 2012, 18:09   #68
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Quote:
Originally Posted by billt View Post
Will this adapter ever be for sale? I'd love to buy one.
I would rather ask - will you ever make an accelerator based on the altera FPGA - this would be far more interesting for most of us.
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Old 03 May 2012, 20:53   #69
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Quote:
Originally Posted by Nikodem View Post
I would rather ask - will you ever make an accelerator based on the altera FPGA - this would be far more interesting for most of us.
So long as I could reprogram it as I please to play with my own ideas, a "true accelerator" board would be fine too. And I wouldn't limit to Altera. Just say FPGA. I don't think that the RTL class I'm taking now has made me Xilinx-specific, but Spartan3e is what I've put simple things into myself now. (I also have a DE1, but haven't fiddled with it or the Quartus tools yet) I'd want the most appropriate FPGA available, regardless of brand.
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