Maximum blitter speed with pipelining

[Toni Wilen]

Originally Posted by dissident

But apart from this I know that the overclocked 68060/83 Mhz CPU of my friend behaves different. Setting the BLTPRI-bit for my routines freezes this machine. Maybe the whole clock/bus handling is messed up there or incompatible due to the fact of overclocking.

Overclocked systems don't count, at least without ability to switch back to original clocks to confirm possible hardware fault. Even if they are supposedly stable in "normal" use. Timing glitches can happen too easily, timing logic is rarely designed for (much) higher clocks, even if all chips are fast enough.

Originally Posted by frank_b

Hi Toni.

Can you please describe how the arbitration works in blit nice mode? The HRM mentions that the blitter yields for one cycle (slot?) if the CPU is halted for several cycles. What happens if there are idle cycles in the blit? Can the CPU realign to use them? Will the blitter yield if the CPU is blocked by other DMA? I wonder if it would be worthwhile to use blitnice mode if the CPU is doing multiplies or divide instructions.

Will the CPU get cycles if blocked by just the blitter? Do other DMA channels count in this case?

It has technically not much to do with blitter cycles. (Perhaps it did in some very early design?)

If CPU memory access is blocked due to any (not just blitter) Agnus/Alice DMA channel, Gary/Gayle internal counter is increased. Each time CPU gets the cycle, counter is reset. If counter has counted to 4 (max) and cycle is blitter cycle: CPU can use the cycle.

Above algorithm is not based on any hardware diagrams (so far no one has found any), I just tried different methods years and years ago until I found one that works and is very simple. It has worked perfectly with all programs, including testing real hardware with logic analyzer.

[Photon]

Originally Posted by dissident

What I can’t understand is the fact that running my routines out of FAST memory on a 68060 with the BLTPRI-Bit turned on, the blitter controlled by the copper, needs more time to execute. Yes, I know that most accelerators are slower accessing CHIP-memory than the original 68020 CPU. And yes, the CPU has to clear the picture which is CHIP memory and has to update the copperlist which is also in CHIP memory. But the blitter in this case has full priority over the CPU. To my mind, this should have no effect at all, if I'm not totally wrong.

Originally Posted by Toni Wilen

Exact same blitter start position in both tests? Exact same other (copper, bitplanes, same fmode etc) DMA channel usage in both tests?

As Toni hints, to compare execution speeds, make sure you're starting the blit with the same competition from other DMA - i.e. bitplane DMA. Start them both at the vertical blank or a given rasterwait, and the blit will finish at the same time as long as the number of bitplanes displayed isn't different between the tests. Otherwise you can't compare the results fairly.