Schematics of custom Amiga chip internals?

[NorthWay]

I saw a comment somewhere on how it could perhaps be possible to train an AI thingie to learn what different logic gates look like, and from that put together and build up a logic working of a decapped IC.

[talybont]

Originally Posted by NorthWay

I saw a comment somewhere on how it could perhaps be possible to train an AI thingie to learn what different logic gates look like, and from that put together and build up a logic working of a decapped IC.

Maybe you are referring to this: http://eab.abime.net/showthread.php?t=102583



The possibilities are endless, but just because someone can imagine it doesn't mean it will be easy to do. Someone still needs to do some actual work. If the person in question has actual abilities beyond fantasy remains to be seen.

[coldacid]

Not to mention that AI processing of the die photos would result in a nice electrical diagram but not necessarily the logic diagram desired for figuring out how to reimplement everything in an FPGA.

[NorthWay]

Originally Posted by coldacid

Not to mention that AI processing of the die photos would result in a nice electrical diagram but not necessarily the logic diagram desired for figuring out how to reimplement everything in an FPGA.

It would be a nice start simply recognizing regular logic like AND, OR, NOT, EOR etc and then step up to adders, shifters, multipliers, and so on.

I'd like to think of it as a visual equivalent to ReSource where the program logic finds all the singularities and does its best to stitch together logic, and you can come in with your human knowledge and mark out parts or whole blocks for what they do. The AI portion should learn more the more ICs it sees.

[coldacid]

I'm talking about the logic primitives, though.

[talybont]

Cool, so who will start the ball rolling?

[PurpleMelbourne]

The AI sounds like a great idea. How about the 6800 series and then onto the 68000 series.
But also there might be pre 6800 stuff done in a similar style which would also be good for the AI to start learning first.

Does anyone here already know AI? It wouldn't be the first time that Amiga users learn an entirely new field so as to apply it to the beautiful machine.

[MoonDragn]

really just need a program to turn the different layers into P and N for decoding the silicon, then a matter of converting it to their respective schematic representations. Assuming each component is isolated from another in the layers and assuming you can figure out which layer is which and which ones are the signal carrying layers. Not sure you can do it by picture alone, you would need to take a sample of each layer and process them.

[pandy71]

Originally Posted by MoonDragn

really just need a program to turn the different layers into P and N for decoding the silicon

There is new Open Source DeGate https://github.com/DegateCommunity/Degate/ but all layers need to be available as pictures (metalization removed). Anyway tgether with already avaiable IC schematics at https://github.com/nonarkitten/amiga...cement_project it should be possible to get accurate transistor / gate FPGA representation.

[fpgaarcade]

It was me (Mike@fpgaarcade) who delivered the chips to the guy who does siliconpr0n during a business trip a few years ago. We've been working to reverse engineer the die shots for a while and I believe we are close.
I'll update you asap, and yes it will be public.
/Mike

[fpgaarcade]

Interestingly, the original three chips (Agnus, Paula and Denise) are made with an NMOS process. Gary and Lisa were CMOS.


It's not trivial to turn an image into a netlist. It's a bit harder to extract gates from that netlist. The real issue is turning what is a sea of basic cells (think NOR / INV etc) into some RTL code - it's time consuming and error prone.


There are tools you can use to check logical equivalence between the two designs. So, I think we will capture the original logic one day.

[simon_m74]

I hope that the Amig chips can be remade soon!

[jasonsbeer]

Originally Posted by fpgaarcade

It was me (Mike@fpgaarcade) who delivered the chips to the guy who does siliconpr0n during a business trip a few years ago. We've been working to reverse engineer the die shots for a while and I believe we are close.
I'll update you asap, and yes it will be public.
/Mike

This is great news. Thank you for your work!

[kamelito]

IIRC some diagrams (was it Agnus?) leaked some years ago.

[jasonsbeer]

Originally Posted by kamelito

IIRC some diagrams (was it Agnus?) leaked some years ago.

Schematics of the original Agnus and other custom Amiga ICs are out there.

https://github.com/nonarkitten/amiga...cement_project

[NorthWay]

There seems to be several projects to document, deconstruct and rebuild all the chips. It could be interesting making a thread (or website?) tracking the existence and progress of these. Do anyone have a rough guesstimate at where we are at?

[jbilander]

These are the current re-implementations that I know of at the time of writing:

Denise (Martin Åberg, https://github.com/endofexclusive/deniser)
Gary (Matthias Heinrichs, https://gitlab.com/MHeinrichs)
Buster (Matt Harlum, https://github.com/LIV2/Bluster)
CIA (Niklas Ekström, https://github.com/niklasekstrom/cia-verilog)
Agnus (https://github.com/jbilander/ReAgnus) Niklas Ekström has a prototype working.
Paula (https://github.com/nonarkitten/amiga.../paula/Paula.v) Frederic Requin mentioned that his implementation can work as a stand-alone chip.

[NorthWay]

Thanks!
Somewhere in the back of my head I have a feeling there is at least one more Gary project? And I don't know if they are the same, but I'm pretty sure I have seen mention of CIA replacements under the names of both FBI and KGB?

What is lacking then? Super Buster (Dave Haynie v12 on the backburner due to chip shortages), Lisa, Alice?

[NorthWay]

So I found what was lurking in the back of my head as regards CIA projects. Someone on Hackaday referenced these 3 links for CIA based projects. I don't know if they are related or dead or usable?
https://1nt3r.net/j-cia/
https://www.forum64.de/index.php?thr...-via-pia-fpga/
https://github.com/bwack/VHDL6526