Low-level workings of Paula

[absence]

Originally Posted by pandy71

Why?
This is circuit with two DAC's in series and one of them can be bypassed.

PWM and DAC are not the same. There is nothing analogue about the PWM, so it doesn't make sense to compare it do a digital-to-analogue converter. The PWM signal is generated digitally and is used to amplitude modulate the digital audio with "and" gates before it's sent to the DAC.

Originally Posted by pandy71

Yes, and i never claimed that there is ECS or AGA Paula - verification in ECS or AGA system can be easier due fact that video sequencer is programmable and H line can be shorter thus H frequency higher and DMA data can be feed to Paula faster than 56ksps - then verification for internal architecture should be easier (however i think that at least in theory H line can be shortened also on OCS by access cycle to correct STR* strobe registers). And faster DMA can affect modulation when modulation one channel to another is active - (however only one byte from word is used) - limitations for internal Paula architecture can be easily exposed when H line will be really short.

Sorry, I misunderstood and thought that there was something left you wanted to verify. Maybe faster DMA would make verification easier than slower DMA, but you don't need DMA at all - a latched value (actually two due to the chip design IIRC) revealed the PWM.

[pandy71]

Originally Posted by absence

PWM and DAC are not the same. There is nothing analogue about the PWM, so it doesn't make sense to compare it do a digital-to-analogue converter. The PWM signal is generated digitally and is used to amplitude modulate the digital audio with "and" gates before it's sent to the DAC.

Oh no, they are (PWM) simply different way to have DAC - if PWM DAC have variable Vref it will work as PAM (Pulse Amplitude Modulation) - PWM after integration (low pass filtering) will produce normal analog signal, exactly same as other DAC's - in fact this is one of the so called 1bit converters (PWM and Delta Sigma).

http://www.rane.com/note137.html

Originally Posted by absence

Sorry, I misunderstood and thought that there was something left you wanted to verify. Maybe faster DMA would make verification easier than slower DMA, but you don't need DMA at all - a latched value (actually two due to the chip design IIRC) revealed the PWM.

Hmmm now seems i don't understand. Value stored in AUDxDAT (word - 2 bytes - 2 samples) are repeated when DMA hardware is not capable to provide requested by Paula new data - this will produce variable level 2 pulse signals - if value for this samples will be same only DC level will be produced at the Paula output and this can be used as a reference to be modulated (variable level) by 6 bit value in AUDxVOL (assumption that AUDxVOL will be feed by samples converted to 6 bit however this is very inefficient method due sampling rate limitation - mentioned by Toni 3.58MHz/64/2 = approx 28kHz).

[absence]

Originally Posted by pandy71

Oh no, they are (PWM) simply different way to have DAC - if PWM DAC have variable Vref it will work as PAM (Pulse Amplitude Modulation) - PWM after integration (low pass filtering) will produce normal analog signal, exactly same as other DAC's - in fact this is one of the so called 1bit converters (PWM and Delta Sigma).

What I mean is that you can't have two DACs in series, because the first one converts the digital signal to analogue, and then the second DAC would get analogue signal for its digital input. The volume mechanism is entirely digital - digital input and digital output - by definition not a DAC.

If you want to predict how the volume mechanism affects the sound, you have to look at what it does to the waveform, which is amplitude modulation with a pulse wave.

Originally Posted by pandy71

assumption that AUDxVOL will be feed by samples converted to 6 bit however this is very inefficient method due sampling rate limitation - mentioned by Toni 3.58MHz/64/2 = approx 28kHz

I think we're talking past eachother. The point was to figure out how the volume mechanism works, so the volume register had a constant value, not what you assume.

[pandy71]

Originally Posted by absence

What I mean is that you can't have two DACs in series, because the first one converts the digital signal to analogue, and then the second DAC would get analogue signal for its digital input. The volume mechanism is entirely digital - digital input and digital output - by definition not a DAC.

OK, then i must ask - what kind of reference voltage is used by DAC and what if reference voltage for one DAC will be set by second DAC and what if will start changing reference voltage very fast?

PWM DAC converter is one of many DAC's and DAC's can be connected in series - check multiplying DAC:
http://www.national.com/assets/en/other/ms101157.pdf

"Multiplying DAC: In a sense, every DAC is a multiplying
DAC since the output voltage (or current) is equal to the reference
voltage times a constant determined by the digital input
code divided by 2n (n is the number of bits of resolution).
In a two quadrant multiplying DAC the reference voltage or
the digital input code can change the output voltage polarity.
If both the reference voltage and the digital code change the
output voltage polarity, four quadrant multiplication exists."

Originally Posted by absence

I think we're talking past eachother. The point was to figure out how the volume mechanism works, so the volume register had a constant value, not what you assume.

Oh - is this mean that you are not allowed to change AUDxVOL multiple time per second - perhaps 28000 times per second?

[absence]

Originally Posted by pandy71

OK, then i must ask - what kind of reference voltage is used by DAC

The reference voltage in Paula is constant. I'm note sure what the value is, but you can probably find out in one of the service manuals.

Originally Posted by pandy71

and what if reference voltage for one DAC will be set by second DAC and what if will start changing reference voltage very fast?

Then you get a multiplying DAC. It's an analogue-digital hybrid design which is different from DACs in series. Paula does however not have multiplying DACs, but a purely digital mechanism in the form of PWM, as confirmed by Toni's measurements.

Originally Posted by pandy71

Oh - is this mean that you are not allowed to change AUDxVOL multiple time per second - perhaps 28000 times per second?

The hardware registers can be written to as often as you like. A constant value was simply the best way to figure out how the volume mechanism works.

[pandy71]

Originally Posted by absence

The reference voltage in Paula is constant. I'm note sure what the value is, but you can probably find out in one of the service manuals.

one Vref is constant and is used by one DAC, then output of this DAC is used as Vref in second DAC - There is no spearate Vref input in Puala - thus Paula will never have high quality audio output (unless there is additional voltage conditioning circuit providing Audio Vref but i doubt on this - when Puala was designed no one even think about high quality audio from home computer)

Originally Posted by absence

Then you get a multiplying DAC. It's an analogue-digital hybrid design which is different from DACs in series. Paula does however not have multiplying DACs, but a purely digital mechanism in the form of PWM, as confirmed by Toni's measurements.

Then im curious what is internal topology ie how PWM DAC is connected to AUDxDAT DAC.

btw most of the 1 bit DAC's (even thos high end audio 16 bit converters) are in real life "purelly digital" (like second order DS converters)

Originally Posted by absence

The hardware registers can be written to as often as you like. A constant value was simply the best way to figure out how the volume mechanism works.

I think it can't be updated more frequently than 3.58MHz/64 or you start loosing values (no time for PWM to convert one value - at least 64 cycles required) - this was my point that for AUDxVOL sample rate is 3.58MHz/64 and max allowed frequency is 3.58MHz/128.

[absence]

Originally Posted by pandy71

one Vref is constant and is used by one DAC, then output of this DAC is used as Vref in second DAC

There is no second DAC in Paula.

Originally Posted by pandy71

Then im curious what is internal topology ie how PWM DAC is connected to AUDxDAT DAC.

Each Paula cycle the PWM counter is increased. When the counter is reset when it reaches 64, when AUDxDAT is written, or when DMA starts. When the counter is less than the volume register, each of the 8 audio bits are bitwise anded by 1, otherwise they are anded by 0. The resulting 8 audio bits then go to the DAC.

Originally Posted by pandy71

I think it can't be updated more frequently than 3.58MHz/64 or you start loosing values (no time for PWM to convert one value - at least 64 cycles required) - this was my point that for AUDxVOL sample rate is 3.58MHz/64 and max allowed frequency is 3.58MHz/128.

Oh, now I see that you want to feed a signal to the volume register! Updating the volume more frequently than the PWM period will result in an irregular pulse wave. If you want to feed it a signal with frequencies up to 1/128th of the Paula clock without getting amplitude modulation artifacts, you have to synchronise the register writes with the PWM counter reset as well. The question is why anyone would want to do that.

[pandy71]

Originally Posted by absence

There is no second DAC in Paula.

Is there any official source for this information?

Originally Posted by absence

Each Paula cycle the PWM counter is increased. When the counter is reset when it reaches 64, when AUDxDAT is written, or when DMA starts. When the counter is less than the volume register, each of the 8 audio bits are bitwise anded by 1, otherwise they are anded by 0. The resulting 8 audio bits then go to the DAC.

Is there any official source for this information?

Originally Posted by absence

Oh, now I see that you want to feed a signal to the volume register! Updating the volume more frequently than the PWM period will result in an irregular pulse wave. If you want to feed it a signal with frequencies up to 1/128th of the Paula clock without getting amplitude modulation artifacts, you have to synchronise the register writes with the PWM counter reset as well. The question is why anyone would want to do that.

So there is no sense to do this if AUDxDAT can be feed by Copper to produce audio without DMA and with higher sampling frequency than allowed in OCS.

[absence]

Originally Posted by pandy71

Is there any official source for this information?

Only the hints in the HRM that I mentioned in the summary, which is why Toni did measurements to confirm the theory.

Originally Posted by pandy71

So there is no sense to do this if AUDxDAT can be feed by Copper to produce audio without DMA and with higher sampling frequency than allowed in OCS.

You tell me, I don't know what you want to achieve.

[pandy71]

Originally Posted by absence

Only the hints in the HRM that I mentioned in the summary, which is why Toni did measurements to confirm the theory.

Oh, so i never read anything from Toni that cover this particular aspect how Paula implements this functionality in silicone.

Originally Posted by absence

You tell me, I don't know what you want to achieve.

stereo sound, 8 bit between 64 and 96 ksps.

[absence]

Originally Posted by pandy71

Oh, so i never read anything from Toni that cover this particular aspect how Paula implements this functionality in silicone.

Toni asked me to summarise our private message discussion that originated from this thread and present the results. Sorry if anything was unclear.

Originally Posted by pandy71

stereo sound, 8 bit between 64 and 96 ksps.

You can achieve that by writing to AUDxDAT using the CPU. Doing that will constantly reset the volume counter, so the volume mechanism won't work. Set the volume to 64 to avoid weird results.

[pandy71]

Originally Posted by absence

Toni asked me to summarise our private message discussion that originated from this thread and present the results. Sorry if anything was unclear.

OK, let it be this way. To believe i need to see schematics

Originally Posted by absence

You can achieve that by writing to AUDxDAT using the CPU. Doing that will constantly reset the volume counter, so the volume mechanism won't work. Set the volume to 64 to avoid weird results.

Without processing interrupts? Just write data by Copper to AUDxDAT?

[absence]

Originally Posted by pandy71

OK, let it be this way. To believe i need to see schematics

You want to see original chip schematics from Commodore? Good luck with that.

Originally Posted by pandy71

Without processing interrupts? Just write data by Copper to AUDxDAT?

As long as data gets to the register at the right rate it doesn't matter.

[pandy71]

Originally Posted by absence

You want to see original chip schematics from Commodore? Good luck with that.

http://degate.org/
http://siliconzoo.org/tutorial.html
http://siliconpr0n.org/wiki/doku.php
http://visual6502.org/wiki/index.php?title=Main_Page ( http://visual6502.org/wiki/index.php...our_collection )
http://uvicrec.blogspot.nl/2012/07/s...17r-clock.html

perhaps in some future...

Originally Posted by absence

As long as data gets to the register at the right rate it doesn't matter.

Oh - this great news, my understanding how Paula works in nonDMA mode was wrong - reading HKRM i understand that i need to process interrupts each time when 2 samples are played.
Now You saying that i can set AUDxPER (like 40), set 64 in AUDxVOL and with Copper send all required data and i can ignore interrupts. Is that OK?

[kamelito]

Originally Posted by absence

You want to see original chip schematics from Commodore? Good luck with that.

These schematics?

[ Show youtube player ]

around 1m22s

Kamelito

[absence]

Originally Posted by pandy71

Oh - this great news, my understanding how Paula works in nonDMA mode was wrong - reading HKRM i understand that i need to process interrupts each time when 2 samples are played.
Now You saying that i can set AUDxPER (like 40), set 64 in AUDxVOL and with Copper send all required data and i can ignore interrupts. Is that OK?

I'm not an Amiga programmer, so you'll have to try that and see what happens. All I know is that you can feed it data at higher rates than DMA by using the CPU and writing to AUDxDAT. I believe the details of this are specified in the HRM.

Originally Posted by kamelito

These schematics?

Wow, they still exist? If only the community could get their hands on them...

[pandy71]

Originally Posted by kamelito

These schematics?

[ Show youtube player ]

around 1m22s

Kamelito

Perhaps?

I saw this and i even ask Her about details but no reply - it is sad that She probably will not do anything with these schematics and they will be lost until She or someone decide to make home sale - perhaps then, sad but true...

For now we must do educated guess for how things works - machine seen from programmer point of view can be completely different than HW point of view...

[pandy71]

Originally Posted by absence

I'm not an Amiga programmer, so you'll have to try that and see what happens. All I know is that you can feed it data at higher rates than DMA by using the CPU and writing to AUDxDAT. I believe the details of this are specified in the HRM.

I'm not an Amiga programmer too... so this was my question - is there any chance to obey some DMA limits on OCS with Copper for audio.
I've read HRM and from my understanding interrupts must be correctly processed - CPU is to slow to deal with such things.

Originally Posted by absence

Wow, they still exist? If only the community could get their hands on them...

AFAIR some Commodore documentation for their IC's was lost - perhaps this can be part of this lost documentation (this is strange how you can loose chip documentation)...

[Toni Wilen]

Originally Posted by pandy71

Oh - this great news, my understanding how Paula works in nonDMA mode was wrong - reading HKRM i understand that i need to process interrupts each time when 2 samples are played.
Now You saying that i can set AUDxPER (like 40), set 64 in AUDxVOL and with Copper send all required data and i can ignore interrupts. Is that OK?

You need to clear INTREQ (It can be done with copper) or state machine returns to idle state after period has counted twice to zero instead of starting to play next sample "word". AUDxDAT write with DMA OFF and channel INTREQ bit set: nothing happens.

It is clearly shown in HRM audio state diagram

[mc6809e]

Originally Posted by absence

You can achieve that by writing to AUDxDAT using the CPU. Doing that will constantly reset the volume counter, so the volume mechanism won't work.

Depends I think. Anything above about 56K values per second will change the granularity of the volume control mechanism, but I think some control is still available.

All that seems to happen with faster rates is that the output isn't gated off for the higher volume values as the counter is reset too quickly. For smaller values, the counter should still reach zero at the faster output rates.

For example, if the output rate is slightly above 56K, then there are still about 62 volume levels.

If the output rate is above 100K, then there are about 30 levels.