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Old Today, 09:57   #801
frank_b
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Quote:
Originally Posted by Bruce Abbott View Post
How much faster and with which Fast RAM?
About 20% IIRC. It was a regular fast RAM card. Nothing fancy.
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Old Today, 11:49   #802
roondar
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Quote:
Originally Posted by frank_b View Post
About 20% IIRC. It was a regular fast RAM card. Nothing fancy.
By now I was interested in what was going on and so I wrote a small test program (using CIA timer, OS disabled and forced chip/forced fast code) and ran it using WinUAE cycle exact mode. It did indeed show a difference on shifts even with 0 bitplanes, but it only was about 0,9%.

I'll expand the program to produce readable output and retry on actual hardware, but I'm honestly not expecting the results to change much - if WinUAE was off by that much a bunch of A500 stuff should really fail to run reliably.

This is rather off-topic though, perhaps a new thread would be better?

Last edited by roondar; Today at 12:04.
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Old Today, 13:00   #803
ross
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Quote:
Originally Posted by roondar View Post
This is rather off-topic though, perhaps a new thread would be better?
Well, topic is "68k details" so is not too much off-topic (although in effect this is really Amiga strictly related, but this is an Amiga forum )

Remember that you can disable all DMA but not the memory refresh cycles for chip/bogo RAM,
so the 'not multiple of four' cycles count shift instructions could be delayed.

EDIT:
Slow down estimation for PAL Amiga in chip RAM: 100/227*(4/2)=0,88%
So 0,9% seem a valid result.

Last edited by ross; Today at 13:11. Reason: Added estimation
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Old Today, 13:59   #804
chb
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Wouldn't fast ram also need refresh cycles? Maybe UAE simply does not emulate those, as probably there isn't any software relying on a specific fast ram timing (which could also vary a lot between implementations, take e.g. the slow PCMCIA SRAM...).
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Old Today, 14:17   #805
ross
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Quote:
Originally Posted by chb View Post
Wouldn't fast ram also need refresh cycles? Maybe UAE simply does not emulate those, as probably there isn't any software relying on a specific fast ram timing (which could also vary a lot between implementations
Sure DRAM require refresh, no idea how implemented in various 'real' fast RAM expansions.
Perhaps in a good implementation (with cells fast enough) delays can be negligible.

Quote:
take e.g. the slow PCMCIA SRAM...).
Actually PCMCIA SRAM is slow for other reasons, it do not require refresh.
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Old Today, 14:29   #806
roondar
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Right, I've now run my test program on an actual 68000 powered Amiga with Fast RAM and added a screenshot with the results.

Results are identical to the emulated Amiga: 0 bitplanes slows down shifts by about 0,9%.

For those interested, I've attached the executable so you can run your own test. Note that it does contain a 'minor' bug, after running it's possible the keyboard stops working. This is probably due to me mishandling restoring the CIA registers. That said, the timer is accurate so the important bit does work
Attached Thumbnails
Click image for larger version

Name:	ChipVsFast_small.jpg
Views:	20
Size:	157.1 KB
ID:	60854  
Attached Files
File Type: zip CycleTest.zip (915 Bytes, 3 views)
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Old Today, 14:31   #807
chb
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Quote:
Originally Posted by ross View Post
Actually PCMCIA SRAM is slow for other reasons, it do not require refresh.
Yeah I know, I just had in mind everything that you could stick into the PCMCIA slot, my comment was only related to general timing, not specifically to refresh.

Roondar: Very interesting result! What kind of memory expansion do you use?
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Old Today, 14:52   #808
roondar
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Quote:
Originally Posted by chb View Post
Yeah I know, I just had in mind everything that you could stick into the PCMCIA slot, my comment was only related to general timing, not specifically to refresh.

Roondar: Very interesting result! What kind of memory expansion do you use?
That is on an A600 with a 4MB PCMCIA card. It's the only Amiga with both a 68000 and Fast RAM that I have - my A500 has Fast RAM, but it's on the ACA500 which has a double speed 68000 and that doesn't feel fair.

I'm actually still looking for an affordable way to add sideslot Fast RAM (without a faster CPU) to the A500 for other testing purposes. Though seeing these results fit with WinUAE I guess it's less of a necessity now - I should be able to use the A600 instead.

For reference, my program runs 30000 shifts (asl.w #2,d0) and times the result using the CIA. These should take exactly 10 cycles each, but turn out to take 0,9% more when run in Chip RAM. The result is given in CIA cycles where one CIA cycle is 10 CPU cycles as the CIA runs at 1/10th of the CPU frequency.
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Old Today, 17:55   #809
frank_b
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Hmm.. maybe the 20% increase was with 4 planes active. I did see a difference between running the code from fast RAM and from chip. I'll have a dig about my 1k drive and see if I can find it later this week.
I was using raster timing.
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