BEAMCON0 better description

[Toni Wilen]

ECS/AGA BEAMCON0 has bad, confusing and partially wrong descriptions in aga.guide. Here is attempt to document them better.. (Thanks to ross as usual for test programs etc..)

HARDDIS

Disable DDFSTRT/DDFSTOP hard limits. (SHRES or UHRES BPLCON0 bits also disable these limits)
Disable bitplane vertical diw force close when line=0.
Disable vblank start bitplane vertical diw force close.

LPENDIS

Lightpen trigger won't latch and stop VPOSR,VHPOSR,HHPOSR registers.

VARVBEN

Programmed vertical blank enable. From VBSTRT (+1, it takes 1 line for VB to start) to VBSTOP.
Hardwired start: A1000 Agnus: Line 1. OCS+: Line 0. End: Line 25 (PAL), 20 (NTSC).
Internally also does same as HARDDIS=1, vertical limits only.

LOLDIS

Disable alternating long/short horizontal. Disables LOL even if PAL bit is not set.

CSCBEN

Weird dual display mode.. Probably UHRES related.
If set, programmed CSYNC is connected to HSYNC pin and blanking signal comes from VSYNC pin.
CSYNC pin keeps working normally, outputs hardwired PAL/NTSC CSYNC signal.

VARBEAMEN

Programmed horizontal and vertical counter enable.
Internally also does same as HARDDIS=1, both horizontal and vertical limits.

HTOTAL and VTOTAL active. (PAL/NTSC hardwired comparators disabled)

VARVSYEN

Programmed vertical sync enable. From VSSTRT to VSSTOP.
When VSSTRT matches and LOF=0: VSYNC enables when horizontal positions matches HSSTRT. LOF=1: VSYNC activates when horizontal position matches HCENTER.
When VSSTOP matches and LOF=0: VSYNC disables when horizontal positions matches HSSTRT. LOF=1: VSYNC disables when horizontal position matches HCENTER.

VARHSYEN

Programmed horizontal sync enable. From HSSTRT to HSSTOP.
No special conditions.

VARCSYEN

Programmed composite sync enable. This one is complex..

CSYNC uses programmed VSYNC internally as an input signal. VSYNC state is always programmed VSYNC, even if VARVSYEN=0.

If VSYNC=0:
When HSSTRT matches: CSYNC signal is activated.
When HSSTOP matches: CSYNC signal is deactivated.
HCENTER does nothing.
If VSYNC=1:
When HSSTRT matches: CSYNC signal is activated.
When HBSTRT or HBSTOP matches: CSYNC signal is deactivated. (yes, deactivated, and yes: HBSTRT and HBSTOP!)
When HSSTOP matches: Nothing happens!
When HCENTER matches: CSYNC signal is activated.

This describes only Agnus/Alice side of HBSTRT/HBSTOP when VARVSYEN=1 and VSYNC=1. Denise/Lisa side is something different and Denise and Lisa have different behavior (Denise does not have HBxxxx registers but Lisa does)

DUAL

When set, all horizontal comparators compare against HHPOS, not normal horizontal counter.
(HBSTRT, HBSTOP, HSSTRT, HSSTOP, HTOTAL, HCENTER)
Another (never used?) weird UHRES support bit.

PAL

312/313 vs 262/263 line count. 227 vs 227/228 alternating horizontal counts. (HSync timing is 227.5)
In programmed mode PAL bit also disables alternating horizontal.

BLANKEN

When BLANKEN=1: Agnus/Alice CSYNC output becomes blanking output, activated when HBSTRT matches, deactivated when HBSTOP matches.
When EXTBLKEN=1 and ECS Denise: ECS Denise activates blanking when CSYNC line is active.

ECS Denise does not have HBxxxx registers and for some reason they decided to use CSYNC as blanking line when programmed blanking is enabled (EXTBLKEN=1).
It is totally obsolete in AGA because CSYNC is not connected to Lisa and Lisa has HBxxxx registers and uses HBxxxx contents when EXTBLKEN=1. Feature is not removed, Alice still generates blanking CSYNC when BLANKEN=1.

HSYTRUE

Invert state of HSYNC output pin

VSYTRUE

Invert state of VSYNC output pin

CSYTRUE

Invert state of CSYNC output pin


Note that VARVSYEN, VARHSYEN, VARCSYEN and CBCEN state does not affect Agnus/Lisa internal operations, these bits only select if Agnus/Lisa H/V/C sync output pins output programmed sync or hardwired sync.
Both hardwired and programmed horizontal/vertical logic is always continuously active.

[ross]

Originally Posted by Toni Wilen

Both hardwired and programmed horizontal/vertical logic is always continuously active.

And that's a good thing since the programmed modes are selectable by type; you can also have different source signals on different sync pins.


Thanks for the long description, finally a good reference!