Open-source scsi device

[mfilos]

A4000 IDE controller can work just fine under PIO-2 with the new GALS (code from yaqube iirc)

[Don_Adan]

Originally Posted by mfilos

A4000 IDE controller can work just fine under PIO-2 with the new GALS (code from yaqube iirc)

Do you tested PIO-0 and PIO-2 A4000 IDE controller version for this same HD? Do you know max. transfer for both versions?

[_mandark_]

Originally Posted by Don_Adan

I don't remove/change wait code for now, maybe later it can be changed too. Which speed value occured for v43.45 on your setup?

With v43.45 I get 2290 KB/s.

[SpeedGeek]

Originally Posted by mfilos

A4000 IDE controller can work just fine under PIO-2 with the new GALS (code from yaqube iirc)

The PIO2 hack is not always working fine mfilos my friend.
There is a timing bug which makes the speed of the GALs critical for PIO2 mode. I made a new IDEU901M.jed which helps improve the timing for PIO2 but I have not heard if Yaqube approved of it's distribution yet.

SpeedGeek:
Since Yaqube gave you instructions to solve the PIO2 bug he has also given you permission to test modified versions of his GAL logic. So if the new IDEU901M.jed works then just ask for permission to distribute it!

Cosmos:
Ok, working now on my A4000D : super !!
With two Gal 10ns all is fine, but with 7ns the HD is not detected...
Anyway, if ok with 10ns, it's perfect !!

[Don_Adan]

Next version is available. Reworked Conner CP2024 support routine, removed extra waits for new HD's. Tell me, if any HD don't works anylonger.

[_mandark_]

New version works ok on my setup.

[Don_Adan]

Next version is available, can be a few fastest.

[_mandark_]

Works nicely. But no speed obvious speed difference.

[fgh]

Originally Posted by Don_Adan

MaxTransfer problem is perhaps (I don't have HD to tests this) solved too, then every MaxTransfer value can be used, and perhaps over 128GB HD can be used too (again I don't have this HD for tests)

Cool that you added support for 48-bit LBA.

If you didn't see this already, Toni Wilen found the precise reason for the maxtransfer problem. Maybe it can help you verify your maxtransfer fix.

Which version did you start off from? Original 3.1 or 43.something?
Does this version support NSD, TD64 or both?

[Don_Adan]

Originally Posted by fgh

Cool that you added support for 48-bit LBA.

If you didn't see this already, Toni Wilen found the precise reason for the maxtransfer problem. Maybe it can help you verify your maxtransfer fix.

Which version did you start off from? Original 3.1 or 43.something?
Does this version support NSD, TD64 or both?

This is special version, someone sent to me this version. I think that this version has no maxtransfer problem and has 2TB limit for HD, if bigger HD is connected only first 2TB is visible. It has support for CHS, LBA and LBA 48-bit. I don't know if it has support for NSD or TD64. Someone can check this.

[Don_Adan]

Next version is available. Reworked IdentifyDrive and ReadCapacity routines.

[_mandark_]

Running this version for a few days now and got no problems. Keep up the good work dude!

[Don_Adan]

Originally Posted by _mandark_

Running this version for a few days now and got no problems. Keep up the good work dude!

Thanks for tests.
Next version is available.
Reworked Mode Sense and Request Sense routines.

;ModeSense    BSR.W    IdentifyDrive
;    TST.L    D0
;    BNE.W    SetErrorStatus
;    MOVEA.L    $64(A3),A1
;    LEA    $74(A2),A0        ; identify drive block offset
;    MOVE.B    2(A1),D1
;    BMI.S    lbC002524        ; minus here
;    BTST    #6,D1            ; bclr #6,D1
;    BEQ.S    lbC002524
;    LEA    -$18(SP),SP
;    MOVEA.L    SP,A1
;    MOVEQ    #$18,D0
;    BSR.W    ClearArea
;    AND.B    #$3F,D1            ; not necessary if bclr
;    LSL.W    #8,D1
;    MOVE.B    #$16,D1
;    MOVE.W    D1,(A1)
;    MOVEQ    #$18,D0
;    BRA.W    lbC0025A6

;lbC002524    AND.B    #$3F,D1
;    CMP.B    #3,D1
;    BNE.S    lbC00257E
;    LEA    -$18(SP),SP
;    MOVEA.L    SP,A1
;    MOVEQ    #$18,D0
;    BSR.W    ClearArea
;    MOVE.W    #$316,(A1)
;    MOVEQ    #2,D0        ; Default number of cylinders
;    BSR.W    lbC0025CC
;    MOVE.W    D0,2(A1)
;    MOVEQ    #12,D0
;    BSR.W    lbC0025CC    ; Default number of sectors per track
;    MOVE.W    D0,10(A1)
;    MOVE.W    #$200,12(A1)
;    MOVE.W    #1,14(A1)
;    MOVEQ    #0,D0
;    BSR.W    lbC0025CC    ; General configuration bit-significant information
;    MOVE.B    D0,D1
;    LSL.B    #5,D1
;    AND.B    #$C0,D1
;    BTST    #6,D0
;    BNE.S    lbC002576
;    BSET    #5,D1
;lbC002576    MOVE.B    D1,$14(A1)
;    MOVEQ    #$18,D0
;    BRA.S    lbC0025A6

;lbC00257E    CMP.B    #4,D1
;    BNE.S    lbC0025C2
;    LEA    -$18(SP),SP
;    MOVEA.L    SP,A1
;    MOVEQ    #$18,D0
;    BSR.S    ClearArea
;    MOVE.W    #$416,(A1)
;    MOVE.B    2(A0),4(A1)
;    MOVE.B    3(A0),3(A1)
;    MOVE.B    6(A0),5(A1)
;    MOVEQ    #$18,D0
;lbC0025A6    CLR.L    -(SP)
;    ADDQ.B    #3,D0
;    MOVEA.L    SP,A1
;    MOVE.B    D0,(A1)
;    ADDQ.B    #1,D0
;    MOVE.L    D0,-(SP)
;    BSR.W    CopyData
;    MOVE.L    (SP)+,D0
;    LEA    0(SP,D0.W),SP
;    MOVEQ    #0,D0
;    BRA.W    SetErrorStatus

;lbC0025C2    ASL.W    #8,D1
;    MOVE.W    D1,-(SP)
;    MOVEA.L    SP,A1
;    MOVEQ    #2,D0
;    BRA.S    lbC0025A6

lbC0025CC    MOVE.W    0(A0,D0.W),D0
    ROL.W    #8,D0
    RTS

;ClearArea    MOVE.L    A1,-(SP)
;    BRA.S    lbC0025DA

;lbC0025D8    CLR.B    (A1)+
;lbC0025DA    DBRA    D0,lbC0025D8
;    MOVEA.L    (SP)+,A1
;    RTS

; ModeSense (final version - 9 III 2013)
; input   D0 (not necessary)
; output  D0 (NoError)
; changed D0/D1/A0/A1

ModeSense
    bsr.w    IdentifyDrive
    bne.w    SetErrorStatus
    moveq    #5,D0
ClearMS
    clr.l    -(SP)
    dbf    D0,ClearMS
    move.l    $64(A3),A1
    move.b    2(A1),D1
    bmi.b    MinusMS
    bclr    #6,D1
    bne.b    MainMS
MinusMS
    and.b    #$3F,D1
    cmp.b    #3,D1
    bne.b    NoThreeMS
    move.w    $74+2(A2),D0    ; Default number of cylinders
    rol.w    #8,D0
    move.w    D0,2(SP)
    move.w    $74+12(A2),D0    ; Default number of sectors per track
    rol.w    #8,D0
    move.w    D0,10(SP)
    move.l    #$2000001,12(SP)
    moveq    #70,D0        ; %01000110
    and.b    $74(A2),D0    ; General configuration bit-significant information
    ror.b    #3,D0        ; %11001000
    bclr    #3,D0        ; %11000000
    bne.b    NoSetMS
    bset    #5,D0        ; %11100000
NoSetMS
    move.b    D0,$14(SP)
    bra.b    MainMS

NoThreeMS
    moveq    #2+3,D0
    cmp.b    #4,D1
    bne.b    CopyDataMS
    move.b    $74+2(A2),4(SP)
    move.b    $74+3(A2),3(SP)
    move.b    $74+6(A2),5(SP)
MainMS
    move.w    #$0016,(SP)        ; always same value
    moveq    #$18+3,D0
CopyDataMS
    move.b    D1,(SP)
    clr.l    -(SP)
    move.l    SP,A1
    move.b    D0,(A1)
    addq.b    #1,D0
    bsr.w    CopyData
    lea    $18+4(SP),SP
    bra.w    NoError

;RequestSense    MOVE.B    #1,$5D(A2)
;    MOVE.L    $274(A2),D0
;    LEA    lbW002CA2(PC),A1
;lbC002C52    MOVE.W    (A1),D1
;    BEQ.S    lbC002C5E
;    AND.W    D0,D1
;    BNE.S    lbC002C5E
;    ADDQ.W    #4,A1
;    BRA.S    lbC002C52

;lbC002C5E    MOVE.W    2(A1),D1
;    LEA    -$12(SP),SP
;    MOVEA.L    SP,A1
;    MOVEQ    #$12,D0
;    BSR.W    ClearArea
;    MOVE.B    D1,2(A1)
;    LSR.W    #8,D1
;    MOVE.B    D1,12(A1)
;    MOVE.B    #$70,(A1)
;    MOVE.B    #10,7(A1)
;    LEA    3(A1),A0
;    EXG    A0,A1            ; a1 is odd
;    MOVE.L    $68(A2),D0
;    BSR.W    lbC002EB4

;    MOVE.B    D0,3(A1)        ; called only once
;    LSR.L    #8,D0
;    MOVE.W    D0,1(A1)
;    SWAP    D0
;    MOVE.B    D0,(A1)
;    ADDQ.W    #4,A1

;    MOVEA.L    A0,A1
;    MOVEQ    #$12,D0
;    BSR.W    CopyData
;    LEA    $12(SP),SP
;    MOVEQ    #0,D0
;    BRA.W    SetErrorStatus

;lbW002CA2    dc.w    1        ; bit 0
;    dc.w    $1303
;    dc.w    2            ; bit 1
;    dc.w    $604
;    dc.w    4            ; bit 2
;    dc.w    $2005
;    dc.w    $10            ; bit 4
;    dc.w    $1203
;    dc.w    $20            ; bit 5
;    dc.w    $2806
;    dc.w    $40            ; bit 6
;    dc.w    $1103
;    dc.w    $80            ; bit 7
;    dc.w    $1103
;    dc.w    $100            ; bit 8
;    dc.w    $2105
;    dc.w    $200            ; bit 9
;    dc.w    $502
;    dc.w    $400            ; bit 10
;    dc.w    $4204
;    dc.w    0            ; other bits
;    dc.w    5

; RequestSense (final version - 9 III 2013)
; input   D0 (not necessary)
; output  D0 (NoError)
; changed D0/D1/A0/A1

RequestSense
    move.b    #1,$5D(A2)
    moveq    #-9,D0            ; ignore bit 3
    and.w    $274+2(A2),D0
    lea    ReqSenTable(PC),A0
    lea    20(A0),A1        ; other bits pointer
LoopRS
    lsr.w    #1,D0
    bcs.b    LaterRS
    addq.l    #2,A0
    cmp.l    A0,A1
    bne.b    LoopRS
LaterRS
    clr.l    -(SP)        ; $11-14
    clr.w    -(SP)        ; 13-12
    move.b    (A0)+,(SP)    ; 12(A1)
    clr.l    -(SP)        ; 11-8
    move.w    #10,-(SP)    ; 7-6, 6/7(A1)
    ifne    MC68000
    move.l    $68(A2),D0
    move.b    D0,(SP)        ; 3+3(A1)
    lsr.l    #8,D0
    move.l    D0,-(SP)    ; 5-2, 2(A1)
    else
    subq.l    #4,SP        ; 5-2
    move.l    $68(A2),1(SP)    ; 3(A1)
    endc
    move.b    (A0),(SP)    ; 2(A1)
    move.w    #$7000,-(SP)    ; 1-0, (A1)
    move.l    SP,A1
    moveq    #$12,D0
    bsr.w    CopyData
    lea    $12(SP),SP
    bra.w    NoError

ReqSenTable
    dc.w    $1303            ; bit 0
    dc.w    $604            ; bit 1
    dc.w    $2005            ; bit 2
    dc.w    $1203            ; bit 4
    dc.w    $2806            ; bit 5
    dc.w    $1103            ; bit 6
    dc.w    $1103            ; bit 7
    dc.w    $2105            ; bit 8
    dc.w    $502            ; bit 9
    dc.w    $4204            ; bit 10
    dc.w    5            ; other bits

[NovaCoder]

Hiya Don,

Do you know about the SpeedyIDE BlizKick module? This module patches your scsi.device for more speed as far as I can tell. Can you build this speed-up into your scsi.device? I think the source code is available.

[Don_Adan]

Originally Posted by NovaCoder

Hiya Don,

Do you know about the SpeedyIDE BlizKick module? This module patches your scsi.device for more speed as far as I can tell. Can you build this speed-up into your scsi.device? I think the source code is available.

No, I don't know. But you can make speed tests (for this same HD and for same Amiga config) for SpeedyIDE version and optimised by me version and tell me results. I don't think that SpeedyIDE version can be fastest. I think that this is possible only if longword (move.l or move16) data transfer will be used.

[Don_Adan]

It seems that SpeedyIDE used longword transfer, anyway this is not 100% good idea, due not all HD supported longword transfer, if I remember right. Anyway perhaps I make some tests.

[_mandark_]

Current version also is running fine.

[NovaCoder]

Originally Posted by Don_Adan

It seems that SpeedyIDE used longword transfer, anyway this is not 100% good idea, due not all HD supported longword transfer, if I remember right. Anyway perhaps I make some tests.

Ok, cool

Also, would there be any speed advantage to target 030/060?

[Don_Adan]

Originally Posted by NovaCoder

Ok, cool

Also, would there be any speed advantage to target 030/060?

Perhaps not speed advantage for 68060.
Here are speed results for some scsi device versions for:
Amiga 4000 68060 75MHz

16 bit transfer (latest version) 3,001,000
32 bit transfer (v1) 2,932,000
32 bit transfer (v2) 2,932,000

It seems that 16 bit data transfer is fastest than 32 bit data transfer.
Here are attached 32 bit versions, if someone want to test this. Maybe for
some configs 32 bit transfer can be fastest, I suspected A600 only.
Infos about speed for other Amiga configs can be useful, choose maximum
value from 5 attempts. Speed infos from other scsi device like 43.4x
can be useful too.

[_mandark_]

Results for my A1200 68030 ACA1230-56Mhz (measured with SysSpeed 4.0):

16 bit transfer (latest version) 2.202 KB/s
32 bit transfer (v1) 2.545 KB/s
32 bit transfer (v2) 2.545 KB/s

WELL DONE!!