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Old 12 November 2019, 19:35   #21
mschulz
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Quote:
Originally Posted by Romanujan View Post
How about running this on MiSTer? Would it be possible to utilize it’s chipset implementation in FPGA?
If someone would attempt to port it to the ARM cpu running on MiSTer then yes, why not. I am however focused on other platforms.

Quote:
Originally Posted by Romanujan View Post
Is the MMU support planned?
Not at this moment. Right now complete CPU support including FPU are the main priority. Maybe later, but I am not sure.
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Old 12 November 2019, 19:48   #22
mschulz
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Originally Posted by skan View Post
This is damn cool! I'm eager to see how this project evolves.
I hope it will get to a point where I can transparently run entire m68k AROS on it, without user or developer notifying any difference. The feeling should be to have RasPi with damn fast m68k CPU (at the moment about 1400 SysInfo MIPS on RasPi4)

Quote:
Originally Posted by skan View Post
In simple words, how does it compare to this http://eab.abime.net/showthread.php?t=90316 ?
Bloodline's project is bare metal Amiga hardware emulator using open source CPU emulation (no JIT, though). He aims at running unmodified OS3.x on it. The CPU core out there attempts to emulate different m68k models with better precision.

My project is pure bare metal m68k JIT emulator with speed in mind. It translates entire blocks of m68k code into ARM opcode stream and executes it. The main goal and highest priority is the raw CPU speed, therefore it unrolls loops if possible, attempts to avoid branches to subroutines by inlining them directly, uses dynamic register mapping etc. There are some reductions of emulation precision though. For example, the m68k condition codes are calculated only if the subsequent instruction does not modify them. The fpu will be only 64bit too. There is no emulation of specific m68k model, I just attempt to translate as many opcodes as possible. Besides, the m68k emulation does not create any special m68k address space, e.g. the instruction

Code:
movea.l 4.w, a0
will be most likely translated to something like

Code:
mov r0,#4
ldr r1,[r0]
provided the dynamic register allocator selected r0 to be a temporary register and r1 to be a mapped m68k's A0 register.
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Old 12 November 2019, 19:50   #23
mschulz
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Originally Posted by Marlon_ View Post
Also, bloodline and mschulz has communicated about this stuff before: http://eab.abime.net/showthread.php?t=96407

Specific comment touching this subject: http://eab.abime.net/showpost.php?p=1306277&postcount=4
Exactly. Funny to say, the "toy" idea, i.e. running the m68k emulation on RasPi directly seems to be now the main idea behind the project - instead of running ARM BE AROS on RasPi there will be M68K AROS on RasPi
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Old 12 November 2019, 19:53   #24
Marlon_
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Quote:
Originally Posted by mschulz View Post
instead of running ARM BE AROS on RasPi there will be M68K AROS on RasPi
Why not both?
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Old 12 November 2019, 20:16   #25
skan
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Quote:
Originally Posted by Marlon_ View Post
Why not both?
This.

...and seamless JanusUAE integration.
Well, THAT would be a perfect NG Amiga... for just 50 bucks!
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