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Old 03 December 2007, 01:41   #61
Zetr0
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@Chain

use the force..... use the force...


I find an impact hammer on high is a fix or f*ckit result.... generally the latter
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Old 03 December 2007, 02:46   #62
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Quote:
Originally Posted by Azryl View Post
Guys, please keep us informed on how this is going

I also have an A500 Rev6a with the ram soldered to the mobo in between the original chips. Gives 1meg chip ram but I would also like to have the extra 512k memory board.

I have the AdIDE 40 under the 68000 atm and I need some extra ram to make some games work on this A500

Az
I also have a rev 6a A500 with 1MB chip soldered on the board. How can I add some fast mem to the expantion slot? An A500+ mem expansion card maybe???
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Old 04 December 2007, 21:59   #63
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@Chain

use the force..... use the force...

forced to post this OT pic (while workin on battery replacements)

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Old 04 December 2007, 23:32   #64
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its still Hardware Pron
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Old 08 December 2007, 14:02   #65
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http://chain.3dgrafika.cz/temp/crashfast.jpg

can someone comment my question marks in this scan? (my notices)
(ive also renamed it properly)

on that scanned ptoho seems to be connected all pins of JP3, but WHYDAMMIT!
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Old 08 December 2007, 14:10   #66
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just a stab in the dark...

is that IC1[3]

A] just pulling the signal to ground ?
B] equating both 'lows' to a signal ?

on U35 pin 8

I think the reason for the CNX 38 (with a 68r pull down) is if you are jumpering the other two lines CNX38 , I haven't checked but is CNX a clock or timer signal?
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Old 08 December 2007, 14:34   #67
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Quote:
Originally Posted by Chain View Post
http://chain.3dgrafika.cz/temp/crashfast.jpg

can someone comment my question marks in this scan? (my notices)
(ive also renamed it properly)

on that scanned ptoho seems to be connected all pins of JP3, but WHYDAMMIT!
It is unused gate. Interestingly only one input is set to gnd. All unused inputs MUST be grounded or set +5v or there can be random glitches.
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Old 08 December 2007, 14:41   #68
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Quote:
Originally Posted by Zetr0 View Post
just a stab in the dark...

is that IC1[3]

A] just pulling the signal to ground ?
B] equating both 'lows' to a signal ?
that make sense
Quote:
Originally Posted by Zetr0 View Post

on U35 pin 8

I think the reason for the CNX 38 (with a 68r pull down) is if you are jumpering the other two lines CNX38 , I haven't checked but is CNX a clock or timer signal?
CNX38 means CoNnector eXpansion, pin 38,
which is RAS for expansion ram (cutted from U35 and feeded from crashfast circuitry)

still dont get it how its connected on that photo, there are no connections to U35:15 (source of ras0) and U35:2 (source of ras1)
instead there are two wires to absolutly isolated jp3 pins??? doesnot make sense at all
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Old 08 December 2007, 15:41   #69
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instead there are two wires to absolutly isolated jp3 pins??? doesnot make sense at all
All 4 JP3 pads are connected. Both my rev6 A500 and rev6 schematics agree.
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Old 08 December 2007, 18:43   #70
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All 4 JP3 pads are connected. Both my rev6 A500 and rev6 schematics agree.
The A500 is a 4-layer board.
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Old 08 December 2007, 21:46   #71
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Quote:
Originally Posted by Toni Wilen View Post
All 4 JP3 pads are connected. Both my rev6 A500 and rev6 schematics agree.
i mean after you cut traces as in schematics

Last edited by Chain; 08 December 2007 at 21:54.
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Old 08 December 2007, 22:20   #72
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i mean after you cut traces as in schematics
Ah, now I understood. Checked A500 schematics again and now I see the difference between big image and schematics scan.

U35 is buffer chip, big image uses U35 output pins for RAS0/RAS1 but schematics image uses input side pins. They are functionally same but use different pinout. (perhaps input-side was better idea because buffer chip will add small delay)
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Old 10 December 2007, 19:07   #73
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bloody hell, buffered or unbuffered it still badly crashes
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Old 18 January 2008, 23:19   #74
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*bump*
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Old 19 January 2008, 00:16   #75
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Lightbulb

Maybe I'm wrong, but the "A601" I built use the RAS_1 for the expansion and the RAS_0 is intended only for internal memory.

So, use the RAS_0 for enabling the RAM on the board.
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Old 26 February 2012, 21:11   #76
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I don't see the images in this topic and I'm facing a similar probelm. What I have to do to have an 1MB Chip RAM on the motherboard and an usable FastRAM in trapdoor slot? Or at least to be able to use an KCS Power PC (an PC/XT emulator) in the trapdoor slot.

Thank you in advance guys.
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Old 22 March 2012, 10:27   #77
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Works :)

I have built this and it works (so far). See attached pictures. I used surface mounted "F"-chips. Ramchips are vanilla 120ns. All unused inputs pulled to ground.

I have created a pair of "big" LHA archives to RAM: and so far they pass CRC checks.
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Old 23 March 2012, 20:45   #78
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Awesome!! it is great that some one got this to finally work! any extra info would be greatly appreciated....

Az
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Old 27 March 2012, 08:30   #79
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Awesome!! it is great that some one got this to finally work! any extra info would be greatly appreciated....

Az
It was too early to celebrate. It is really flaky as soon as there is more load on the system.. I may have an idea what it is supposed to do, I'll try another design.
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Old 01 April 2012, 23:17   #80
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Now maybe

Have I cracked this SOB? ?

The DBR* line goes low when the Agnus DMA accesses to the chip ram and up again when it does not. This hack distributes the RAS signaling to the correct membanks depending on the A23 and DBR*.

This hack also needs to consider the RAS refresh that happens on every rasterline, otherwise the memorychips will forget what they have stored. It seems that when it is time for this refresh, both RAS0 and RAS1 goes low. ( RAS is an active low signal btw. ) It it also seems that this is the only time both RAS:es are low, critical for this hack to work.

I hooked up my ancient scope to notice that the DBR* and RAS accesses were not aligned at all. (probably because of long propagation delays inside the agnus..) So basicly there is not a big chance for this hack to work as it is in the finnish magazine imho.

The DBR* needs to be aligned and I did it with 8 OR-gates in series. ( 74LS32, that was the slowest chips I had at hand )

A bit weird that this hack still works at all. I thought Pekka had taken the wrong RAS(0) to the signal he calls RAF0 in the schematic, I think it has to be RAS1 . But there is so much inverting logic going on so I may have missed something. (quite optimized I have to say..)

First screenshot, lower line = original DBR*, upper delayed DBR (closer to 100ns delayed)

Second screenshot shows delayed DBR* in relation with chipmem RAS (display refresh). (It may have to be delayed a bit further still?) I'll post a timing diagram of a generic dram chip later..

Third, test with some load on the ram, mainly display updates on first 512kB bank, mod playing on 2nd 512kB bank, Powerpacker doing some crunching in 512kB slowfast mem.

Fourth, "the delay bodge".

So let's see if this all still works tomorrow.. I didn't know that much about DRAMs or propagation delays before I started investigating this, it has been interesting to say at least..
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