Amiga 500 68K Accelerator - DIY

[PR77]

@Plasmab, I'm thinking about adding another 1Mbyte to my development board and having a go with a MapROM type KS remapping (I would have to write some code to actually copy the KS to FastRAM and then trigger the remap). Have you considered this for your TF designs?

@All, Anyone know the "real life" benefit of this and noticeable speed increase on a 16 Bit bus system (A500, A1000 and A2000) (on my A1200 I have this but to be honest I can't really tell the difference).

[plasmab]

Originally Posted by PR77

@Plasmab, I'm thinking about adding another 1Mbyte to my development board and having a go with a MapROM type KS remapping (I would have to write some code to actually copy the KS to FastRAM and then trigger the remap). Have you considered this for your TF designs?

@All, Anyone know the "real life" benefit of this and noticeable speed increase on a 16 Bit bus system (A500, A1000 and A2000) (on my A1200 I have this but to be honest I can't really tell the difference).

TBH no. It’s too complex and my designs all have MMUs.

[PR77]

Okey dokey folks! The time has come to spin a new PCB. I got the IDE working with a BUNCH of jumper cables swapping the Data lines around. I am finding my hardware not to be very stable and I am suspecting it is because of bad coupling. Especially with a CF Card connected- I will buffer the IDE Interface with a couple of '245 in my PCB spin. My test Amiga is an A500 Rev5 with KS1.2 (was 40€ so a perfect candidate).

I implemented the IDE based on Matthias Heinrichs' ide.device over at A1K. It is a good simple and fast design, only issue is Auto Booting. I have patched a KS3.1 but currently have no EPROM programmer (I tried to make a Softkick version but the KS Header needs to be updated and I have no idea what to modify here. Any ideas?!?) so this will have to wait. Nevertheless, with a larger CPLD I will be able to support a Gayle also.

[patrik]

Originally Posted by PR77

@All, Anyone know the "real life" benefit of this and noticeable speed increase on a 16 Bit bus system (A500, A1000 and A2000) (on my A1200 I have this but to be honest I can't really tell the difference).

The difference is definately noticeable for a 030 with local ram in a 16-bit bus machine. The difference should be greater with a really fast 68000 as it has no instruction cache to lessen the hit when executing code from the relatively slow kickstart.

[plasmab]

Acceleration of Amigas is all about RAM speed and width. Look at the speed we get from the CD32 by giving it 60ns RAM. The 680x0 series cpus are slow so let’s not make them wait ever

[PR77]

Here is the obligatory 3D model of my Rev 2 design. I will try and route the PCB to support both the MC68000 (DIP64) and MC68(S)EC000 (QFP64) devices. My PCB skills aren't the best (KiCAD is my preferred tool- I find all cloud based EDA packages overkill), so perhaps this is a good point to push the design on GitHub.

I have also added an expansion connector for additional RAM and will breakout as many of the free CPLD pins as possible. I haven't locked in my CPLD pins yet as this should be done to simplify track routing (in my opinion).

2 SPI ports (both Zorro II mapped). I found in my parts bin a bunch of nRF24L01 with nice SMA connectors so that would be pretty cool hooked up to an Amiga! I also found an STA013 (dating back a little as these need an external DAC) for MP3 decoding.

EDIT: Ok, here is the GitHub page... Work in progress... More will come...

https://github.com/PR77/A500_ACCEL_RAM_IDE-Rev-1.git

[pandy71]

There is "VSS mp3-capable sound card, hardware & driver" using STA013 - perhaps you could reuse part of design so no need for separate software http://aminet.net/package/driver/audio/vss .

[tnt23]

@PR77, KiCad rulez!

[PR77]

Anyone out there keen to support with a PCB layout and even placement review???

I've done a bit of re-design to the layout and made the board smaller. Probably can be made even smaller. I removed the second DIP package (dual footprint for the accelerated processor as the last few days highlighted some dodgy MC68010 which I ordered from eBay. As the 68SEC000 TQFNs are the real-deal I will stick with these only moving forward).

3D and KiCad Projects attached. Will be pushed also to the GitHub.

EDIT: CPLD nets have not been assigned to PINs just yet as these can be changed to aid with routing.

[PR77]

Wow, 7th of March was the last post. To be honest I have made little to no progress as my attention pivoted to other tasks. I have revisited the PCB routing only to completely stuff it all up- means I need to restart (I overwrote the KiCAD PCB file)! I have refactored the schematic somewhat as I want to make the PCB smaller (cheaper) than originally planned. I have removed SPI for now, perhaps I add this in Rev 3.

[EzdineG]

Originally Posted by PR77

Wow, 7th of March was the last post. To be honest I have made little to no progress as my attention pivoted to other tasks. I have revisited the PCB routing only to completely stuff it all up- means I need to restart (I overwrote the KiCAD PCB file)! I have refactored the schematic somewhat as I want to make the PCB smaller (cheaper) than originally planned. I have removed SPI for now, perhaps I add this in Rev 3.

Don’t be discouraged! This is a very interesting project; I wish I had more to offer. I could definitely try and help route, but I’m not electrically versed enough to guarantee there wouldn’t be noise issues.

Any way, great work thus far.

[PR77]

Thanks for your words of encouragement. I will take you up on your routing offer! Even just another pair of eyes on the layout would be appreciated. I no PCB guru- I did do PCBs about 15 years ago, but gave up as there were people much better than me. I will PM you the latest data.

[EzdineG]

Originally Posted by PR77

Thanks for your words of encouragement. I will take you up on your routing offer! Even just another pair of eyes on the layout would be appreciated. I no PCB guru- I did do PCBs about 15 years ago, but gave up as there were people much better than me. I will PM you the latest data.

Well, I’ve done a total of 1 board, LOL.

If that doesn’t bother you too much, I’ll have a crack at it as time permits.

Got the info from you.

[PR77]

Ok, finally, I mean finally, I got some time to finish the PCB route. Sure I cheated with the Autorouter but free time at the moment is a luxury at the moment. PCBs have been ordered on DirtyPCBs so I'm interested how they turn out and I made the jelly bean component order. So watch this space for new and exciting new!

[PR77]

So, new PCBs have arrived but the footprint for the CPU is wrong. That means 10 scrap PCBs and back to the drawing board. Was my fault as I didn’t print the layers to check before issuing for production.

I also ordered 10 right angle 68000 relocator boards. I only need a few so if anyone is interested PM me. Not sure on the price. What are people paying for these in € plus postage?

[solidcore]

pr77: sorry to hear about the issues you have had. Good luck on the next batch mate.

[PR77]

Originally Posted by solidcore

pr77: sorry to hear about the issues you have had. Good luck on the next batch mate.

Thanks! Actually I designed the PCB with a TQFP (10x10mm) footprint, but the parts I have on hard are QFP (14x14mm). The MC68SEC000 is actually stated in the datasheet as being available in TQFP but I haven't found a seller.

I actually started on Rev 3 of the PCB a week ago because I outright wasn't happy with the bad auto-route job! … and 4 layers! My Rev 3 PCB is slighter bigger and uses more DIP packages which are much easier to route (and solder).

[PR77]

Ok... Rev 3 PCB finished and submitted for manufacturing... A few changes... RAM changed to DIP (easier to solder, easily available, sure it is only 2MB but this design is no attempt at creating a powerhouse. I really just want to learn and make something I always wanted to do as a kid but had no idea how ) and I added a SPI EEPROM with all D[15...0] lines connecting to the CPLD. Of course now the right footprints have been used!

[PR77]

Got my new boards and populated one. So far no smoke but I have noticed that GARY is asserting /HALT on the MC68SEC000.

Anyone know why GARY asserts /HALT?

[PR77]

Ok, I think I have a bus contention which is causes some very strange behaviour. In the two Saleae captures there is an "OK" and "NOK". The OK is with the original 68000 fitted and the NOK is with my 68SEC000 board.

I don't understand why the R/_W = WRITE towards the end and the /UDS gets out of SYNC. Looking into the EXEC disassembly;

http://wandel.ca/homepage/execdis/exec_disassembly.txt

there is a huge delay loop which should keep the processor busy for a while; without a write cycle. Here is a dump of the Verilog. I don't think the issue is here but perhaps someone can have a look for something stupid I can't see;

`timescale 1ns / 1ps
    
/*
    Revision 0.1 - 03.07.2018
    Update for revision 3 of design.
*/

 module ACCEL_RAM_IDE(

    input RESET,
    input MB_CLK,
    input CPU_CLK,
    
    input CPU_AS,
    output MB_AS,
       
    input MB_DTACK,
    output CPU_DTACK,
    
    output reg MB_E_CLK,
    input MB_VPA,    
    output MB_VMA,
        
    input [2:0]	CPU_FC,
    output [2:0] CPU_IPL,
    output BR,
    output BG,
    output MB_BGAK,
    output BERR,
    output CPU_AVEC,
    input RW,
    input LDS,
    input UDS,
    input HALT,
        
    // IDE
    output IDE_RW,
    output [1:0] IDE_CS,
    output IDE_RESET,
    output IDE_READ,
    output IDE_WRITE,
    
    // RAM
    output [3:0] RAM_CS,
    
    // SPI
    output SPI_CS,
    output SPI_MOSI,
    output SPI_SCK,
    input SPI_MISO,
    
    // SPARE
    output [1:0] SPARE,
    input SPARE_NO_CONNECT,
    
    // Address bus
    input [23:1] ADDRESS,
    
    // Data bus
    inout [15:0] DATA

    );
    
assign BR = 1'bZ;
assign BG = 1'bZ;
assign BERR = 1'bZ;
assign MB_BGAK = 1'bZ;
assign CPU_AVEC = 1'bZ;
assign CPU_IPL = 3'bZZZ;

// --- AUTOCONFIG

reg [2:0] configured = 3'b000;
reg [2:0] shutup = 3'b000;
reg [3:0] autoConfigData = 4'b0000;
reg [7:0] autoConfigBaseFastRam = 8'b00000000;
/*
reg [7:0] autoConfigBaseIOPortA = 8'b00000000;
reg [7:0] autoConfigBaseIOPortB = 8'b00000000;
*/
/*
reg writeStable = 1'b0;
*/

wire DS = LDS & UDS;

wire AUTOCONFIG_RANGE = ({ADDRESS[23:16]} == {8'hE8}) && ~&shutup && ~&configured;
wire AUTOCONFIG_READ = (AUTOCONFIG_RANGE && (RW == 1'b1));
wire AUTOCONFIG_WRITE = (AUTOCONFIG_RANGE && (RW == 1'b0));

wire FASTRAM_RANGE = ({ADDRESS[23:20]} == {autoConfigBaseFastRam[7:4]}) && ~CPU_AS && configured[0];

/*
wire IOPORTA_RANGE = ({ADDRESS[23:20]} == {autoConfigBaseIOPortA[7:4]}) && ~CPU_AS && configured[1];
wire IOPORTA_READ = (IOPORTA_RANGE && (RW == 1'b1) && (DS == 1'b0));
wire IOPORTA_WRITE = (IOPORTA_RANGE && (RW == 1'b0) && (writeStable == 1'b1));

wire IOPORTB_RANGE = ({ADDRESS[23:20]} == {autoConfigBaseIOPortB[7:4]}) && ~CPU_AS && configured[2];
wire IOPORTB_READ = (IOPORTB_RANGE && (RW == 1'b1) && (DS == 1'b0));
wire IOPORTB_WRITE = (IOPORTB_RANGE && (RW == 1'b0) && (writeStable == 1'b1));
*/

// INTERNAL_CYCLE signalling is actually /INTERNAL_CYCLE as expected by Accelerator CPLD.
/*
wire INTERNAL_CYCLE = ~(FASTRAM_RANGE || IOPORTA_RANGE || IOPORTB_RANGE);
*/
wire INTERNAL_CYCLE = ~(FASTRAM_RANGE);

// Generate a Write Stable signal for timing Bus Assertions after UDS || LDS are LOW.
/*
always @(negedge CPU_CLK or posedge CPU_AS) begin
    
    if (CPU_AS == 1'b1)
        writeStable <= 1'b0;
    else begin
    
        if ((CPU_AS == 1'b0) && (RW == 1'b0) && (DS == 1'b0))
            writeStable <= 1'b1;
        else
            writeStable <= 1'b0;
    end
end
*/

// AUTOCONFIG cycle.
always @(negedge DS or negedge RESET) begin
    
    if (RESET == 1'b0) begin
        configured[2:0] <= 3'b000;
        shutup[2:0] <= 3'b000;
        autoConfigBaseFastRam[7:0] <= 8'h0;
        /*
        autoConfigBaseIOPortA[7:0] <= 8'h0;
        autoConfigBaseIOPortB[7:0] <= 8'h0;
        */
    end else begin

       if (AUTOCONFIG_WRITE == 1'b1) begin
            // AutoConfig Write sequence. Here is where we receive from the OS the base address for the RAM.
            case (ADDRESS[7:1])
                8'h24: begin

                    if (configured[2:0] == 3'b000) begin
                        autoConfigBaseFastRam[7:4] <= DATA[15:12];     // FastRAM
                        configured[0] <= 1'b1;
                    end
                    
                    /*
                    if (configured[2:0] == 3'b001) begin
                        autoConfigBaseIOPortA[7:4] <= DATA[15:12];     // IO Port A
                        configured[1] <= 1'b1;
                    end
                    
                    if (configured[2:0] == 3'b011) begin
                        autoConfigBaseIOPortB[7:4] <= DATA[15:12];     // IO Port B
                        configured[2] <= 1'b1;
                    end
                    */
                end

                8'h25: begin
                    if ({configured[2:0] == 3'b000}) autoConfigBaseFastRam[3:0] <= DATA[15:12];   // FastRAM
                    /*
                    if ({configured[0] == 1'b1}) autoConfigBaseIOPortA[3:0] <= DATA[15:12];       // IO Port A
                    if ({configured[1] == 1'b1}) autoConfigBaseIOPortB[3:0] <= DATA[15:12];       // IO Port B
                    */
                end

                8'h26: begin
                    if ({configured[0] == 1'b1}) shutup[0] <= 1'b1;   // FastRAM
                    /*
                    if ({configured[1] == 1'b1}) shutup[1] <= 1'b1;   // IO Port A
                    if ({configured[2] == 1'b1}) shutup[2] <= 1'b1;   // IO Port B
                    */
                end
                
            endcase
        end

        if (AUTOCONFIG_READ == 1'b1) begin
            // AutoConfig Read sequence. Here is where we publish the RAM and I/O port size and hardware attributes.
           case (ADDRESS[7:1])
                8'h00: begin
                    if ({configured[2:0] == 3'b000}) autoConfigData <= 4'hE;     // (00) FastRAM
                    /*
                    if ({configured[2:0] == 3'b001}) autoConfigData <= 4'hC;     // (00) IO Port A
                    if ({configured[2:0] == 3'b011}) autoConfigData <= 4'hC;     // (00) IO Port B
                    */
                end
                
                8'h01: begin
                    if ({configured[2:0] == 3'b000}) autoConfigData <= 4'h5;     // (02) FastRAM
                    /*
                    if ({configured[2:0] == 3'b001}) autoConfigData <= 4'h1;     // (02) IO Port A
                    if ({configured[2:0] == 3'b011}) autoConfigData <= 4'h1;     // (02) IO Port B
                    */
                end
                
                8'h02: autoConfigData <= 4'h9;     // (04)  
                
                8'h03: begin
                    if ({configured[2:0]} == {3'b000}) autoConfigData <= 4'h8;     // (06) FastRAM
                    /*
                    if ({configured[2:0]} == {3'b001}) autoConfigData <= 4'h9;     // (06) IO Port A
                    if ({configured[2:0]} == {3'b011}) autoConfigData <= 4'hA;     // (06) IO Port B
                    */
                end

                8'h04: autoConfigData <= 4'h7;  // (08/0A)
                8'h05: autoConfigData <= 4'hF;
                
                8'h06: autoConfigData <= 4'hF;  // (0C/0E)
                8'h07: autoConfigData <= 4'hF;
                
                8'h08: autoConfigData <= 4'hF;  // (10/12)
                8'h09: autoConfigData <= 4'h8;
                8'h0A: autoConfigData <= 4'h4;  // (14/16)
                8'h0B: autoConfigData <= 4'h6;                
                
                8'h0C: autoConfigData <= 4'hA;  // (18/1A)
                8'h0D: autoConfigData <= 4'hF;
                8'h0E: autoConfigData <= 4'hB;  // (1C/1E)
                8'h0F: autoConfigData <= 4'hE;
                8'h10: autoConfigData <= 4'hA;  // (20/22)
                8'h11: autoConfigData <= 4'hA;
                8'h12: autoConfigData <= 4'hB;  // (24/26)
                8'h13: autoConfigData <= 4'h3;

                default: 
                    autoConfigData <= 4'hF;

            endcase
        end
     end
end

// Output specific AUTOCONFIG data.
assign {DATA[15:0]} = (AUTOCONFIG_READ == 1'b1) ? autoConfigData : 16'bZZZZZZZZZZZZZZZZ;

// RAM control arbitration.
assign RAM_CS[0] = ~(FASTRAM_RANGE && ~LDS);
assign RAM_CS[1] = ~(FASTRAM_RANGE && ~UDS);
assign RAM_CS[2] = 1'bZ;
assign RAM_CS[3] = 1'bZ;

// --- MC6800 Emulator

reg [3:0] eClockRingCounter = 'h4;
reg MC6800VMA = 1'b1;
reg MC6800DTACK = 1'b1;

wire CPUSPACE = &CPU_FC;

// Let's get the 709379 Hz E_CLOCK out the way by creating it from the motherboard base 7MHz Clock.
always @(posedge MB_CLK) begin
    
    if (eClockRingCounter == 'd9) begin
        eClockRingCounter <= 'd0;
        
    end else begin
    
        eClockRingCounter <= eClockRingCounter + 'd1;

        if (eClockRingCounter == 'd4) begin
            MB_E_CLK <= 'b1;       
        end

        if (eClockRingCounter == 'd8) begin
            MB_E_CLK <= 'b0;
        end
    end
end

// Determine if current Bus Cycle is a 6800 type where VPA has been asserted.
always @(posedge MB_CLK or posedge MB_VPA) begin

    if (RESET == 1'b0) begin
        MC6800VMA <= 1'b1;
    end

    if (MB_VPA == 1'b1) begin
        MC6800VMA <= 1'b1;
    end else begin

        if (eClockRingCounter == 'd9) begin
            MC6800VMA <= 1'b1;
        end

        if (eClockRingCounter == 'd2) begin
            MC6800VMA <= MB_VPA | CPUSPACE;
        end
    end
end

// Generate /DTACK if 6800 Bus Cycle has been emulated (generatedVMA).
always @(posedge MB_CLK or posedge CPU_AS) begin
    
    if (RESET == 1'b0) begin
        MC6800DTACK <= 1'b1;
    end
    
    if (CPU_AS == 1'b1) begin
        MC6800DTACK <= 1'b1;
    end else begin
               
        if (eClockRingCounter == 'd9) begin
            MC6800DTACK <= 1'b1;
        end

        if (eClockRingCounter == 'd8) begin
            MC6800DTACK <= MC6800VMA;
        end
    end 
end

assign MB_VMA = MC6800VMA;

// --- Accelerator

reg delayedMB_AS = 1'b1;
reg delayedMB_DTACK = 1'b1;
reg fastCPU_DTACK = 1'b1;

// Shift /CPU_AS into the 7MHz clock domain gated by /INTERNAL_CYCLE.
// Delay /MB_DTACK by 1 7MHz clock cycle to sync up to asynchronous CPU_CLK.
always @(posedge MB_CLK or posedge CPU_AS) begin
    
    if (CPU_AS == 1'b1) begin
        delayedMB_DTACK <= 1'b1;
        delayedMB_AS <= 1'b1;
    end else begin
    
        delayedMB_AS <= CPU_AS | ~INTERNAL_CYCLE;
        delayedMB_DTACK <= MB_DTACK;
    end
end

// Generate a fast DTACK for accesses in Interal Space (FastRAM, IO Ports, etc)
always @(posedge CPU_CLK or posedge CPU_AS) begin
    
    if (CPU_AS == 1'b1) begin
        fastCPU_DTACK <= 1'b1;
    end else begin
    
        fastCPU_DTACK <= INTERNAL_CYCLE;
    end
end

assign CPU_DTACK = delayedMB_DTACK & fastCPU_DTACK & MC6800DTACK;
assign MB_AS = delayedMB_AS;

// --- Debug

assign SPARE[0] = CPU_DTACK;
assign SPARE[1] = CPU_AS;

endmodule

I only have the KS1.2 ROM installed. Even if I had DiagROM installed not enough code would be executed to do anything anyway. Things seem to go pear-shaped after the 7th bus cycle.

Any ideas?