Kickstart ROM Address Range(s) - Page 2

thebajaguy · 10 September 2018, 00:09

@ Ross - I know it wasn't totally safe going above C7FFFF, but simply an option to get things working, and better than conflicting with legal expansion areas.

FWIW - Kickstart will auto-map any contiguous RAM @ $00C00000 up to $00DBFFFF, although the A600/1200 have Clockport/IDE appearing here, and some 3rd party clones of the Gayle interfaces place registers here, too.

PR77 · 10 September 2018, 08:53

I haven't tested the Verilog yet, but it currently with Autoconfig 512K legally when needing to program the FLASH chips. When no programming is necessary then the Autoconfig cycle (after reset) will not occur (this has no been implemented yet to ensure I can test).

I have been considering more the 64K (or 128K) IO Space option and the current CPLD pinning would support this. Most likely I will have to use the XC9572 for this; additionally with an appropriate E Cycle counter to time a /RESET of 1 second I need about 20 bits and with an Autoconfig strategy which supports an arbitrary base address the XC9536 is just too small.

P.S., removing all the Autoconfig and fixing the FLASH base address would make the logic fit is a smaller CPLD, this may still eventuate. The CPLD pinning will still work this this (I believe). The beauty with OS is that you and also tinker.

Just gotta find some time now to do the PCB.

PR77 · 13 September 2018, 20:20

So, I ordered some DIP AM29F040B (used these many moons ago when developing PC/104 HW along with the AM186ES) and some nice portable C code functions to control the FLASH. Waiting on these to arrive from China (let's see what I actually get).

I will prototype with my Rev 1 Amiga 500 Accelerator Dev. Board (check out my Git). Also corrected an issue in the Verilog which was not asserting the /DTACK for GARY override addresses (when /AS is not asserted on the MB as the FLASH kickstart is being accessed) with 0WS. So, it should not be any slower than an existing ROM.

PR77 · 10 January 2019, 21:47

After a few months I finally got some time to revisit this little project. Check out the latest here;

https://github.com/PR77/68000_Relocator_FLASH_Kickstart

PR77 · 20 May 2019, 22:21

I've made several updates and now have a final PCB. Check out the GitHub for those interested.

PR77 · 30 March 2021, 21:43

I've seen a few of these boards pop up on eBay and some classifieds here in Germany. I was pleasantly surprised to be honest. Interested to know if anyone here has made one and how they are finding it?

https://github.com/PR77/68000_Relocator_FLASH_Kickstart

30 March 2021, 21:43	#26
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	I've seen a few of these boards pop up on eBay and some classifieds here in Germany. I was pleasantly surprised to be honest. Interested to know if anyone here has made one and how they are finding it? https://github.com/PR77/68000_Relocator_FLASH_Kickstart Last edited by PR77; 30 March 2021 at 21:43. Reason: Added Github link.

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10 September 2018, 00:09	#21
thebajaguy Registered User Join Date: Mar 2017 Location: Rhode Island / United States Posts: 201	@ Ross - I know it wasn't totally safe going above C7FFFF, but simply an option to get things working, and better than conflicting with legal expansion areas. FWIW - Kickstart will auto-map any contiguous RAM @ $00C00000 up to $00DBFFFF, although the A600/1200 have Clockport/IDE appearing here, and some 3rd party clones of the Gayle interfaces place registers here, too.

10 September 2018, 08:53	#22
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	I haven't tested the Verilog yet, but it currently with Autoconfig 512K legally when needing to program the FLASH chips. When no programming is necessary then the Autoconfig cycle (after reset) will not occur (this has no been implemented yet to ensure I can test). I have been considering more the 64K (or 128K) IO Space option and the current CPLD pinning would support this. Most likely I will have to use the XC9572 for this; additionally with an appropriate E Cycle counter to time a /RESET of 1 second I need about 20 bits and with an Autoconfig strategy which supports an arbitrary base address the XC9536 is just too small. P.S., removing all the Autoconfig and fixing the FLASH base address would make the logic fit is a smaller CPLD, this may still eventuate. The CPLD pinning will still work this this (I believe). The beauty with OS is that you and also tinker. Just gotta find some time now to do the PCB.

13 September 2018, 20:20	#23
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	So, I ordered some DIP AM29F040B (used these many moons ago when developing PC/104 HW along with the AM186ES) and some nice portable C code functions to control the FLASH. Waiting on these to arrive from China (let's see what I actually get). I will prototype with my Rev 1 Amiga 500 Accelerator Dev. Board (check out my Git). Also corrected an issue in the Verilog which was not asserting the /DTACK for GARY override addresses (when /AS is not asserted on the MB as the FLASH kickstart is being accessed) with 0WS. So, it should not be any slower than an existing ROM.

10 January 2019, 21:47	#24
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	After a few months I finally got some time to revisit this little project. Check out the latest here; https://github.com/PR77/68000_Relocator_FLASH_Kickstart

20 May 2019, 22:21	#25
PR77 Registered User Join Date: Oct 2017 Location: Germany Posts: 193	I've made several updates and now have a final PCB. Check out the GitHub for those interested.

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