25 May 2018, 18:44 | #581 |
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..
Last edited by Megol; 25 May 2018 at 18:51. Reason: Who cares. |
25 May 2018, 18:50 | #582 | |||||||
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We need simply both the carriage (OS/software) and the horse (hardware). But new horses are expensive and there is already a mule, a donkey and a ox in our barn. The mule is kicking, the ox is slow and the donkey is stubborn - but all three are able to draw the carriage. Not as good as a horse would, but that is all we have got for now... Quote:
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alright than. Last edited by Gorf; 25 May 2018 at 23:45. |
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25 May 2018, 19:04 | #583 |
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25 May 2018, 19:08 | #584 | ||||||||||||||||||||||
son of 68k
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Load/store unit has to handle addresses twice as large. And ya better have bigger caches because you have more data to fit. Of course decoder probably has to cope with bigger instruction (larger immediates and addresses). Even branch prediction has to handle larger addresses... Quote:
And that's bad because else it would indeed be a better solution. Quote:
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I don't like writing these things but you started and i could not find a better answer. I know this isn't ideal. Quote:
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Think of 020+ modes. Largest instruction is 22 bytes and would become 38. And bitfields. No way to encode more than 32 bits in the expansion word. Quote:
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But RISC V yes, though it's not what i'd call popular. Btw ARM is used everywhere not for any technical advantage it might possess, but merely because it is easy to licence and build. Quote:
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That's because it is. Don't confuse speed and latency. Quote:
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And decoding can start before instruction size is known (if you have a wealth of logic to spend for decoding all possible combinations and later choose the right one). Quote:
Now load-store has a big problem in comparison : instead of a single instruction, we have 3 - and they all depend on the result of the previous one ! Quote:
Yes. No. It was only a vague theory. Belief that complex instructions are not really used is simply wrong. Net result : lots and lots of useful stuff removed. |
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25 May 2018, 19:17 | #585 | ||||
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So thanks! Quote:
reading this and your answer to meynaf it strikes me as an interesting concept. I have to admit I never did a single line in 64-bit asm, so I can not judge how bad this would be - but as you said, it should be possible to code within a 32-bit range and the developer would not see a single 64-bit pointer... Quote:
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25 May 2018, 19:18 | #586 | ||
son of 68k
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Besides, as said previously, hardware can be emulated. Quote:
Not understood... Program failed - Error 87000004 Wait for disk activity to finish. Suspend | Reboot (oops i guru meditated too ) Me too and I even replied. |
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25 May 2018, 19:30 | #587 | |||||
son of 68k
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Have i been so rude ? Why destroying posts like this ?
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25 May 2018, 19:30 | #588 | ||
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By the way: OSX is since yesterday "older" than System x.x (older as in longer sold by Apple) Quote:
the only legitimation for some unix code are missing drivers. They could be useful to give us a HAL, without developing drivers ourselves. Otherwise: there are already 1001 unix/posix-clones out there - no need for one more. Last edited by Gorf; 25 May 2018 at 19:42. |
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25 May 2018, 19:33 | #589 |
son of 68k
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25 May 2018, 19:42 | #590 | |
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no really: it is not fast! not compared to the hypothetical native speed. (and that is part of the reason, why I am quite confident the emulation can be improved) And while the OS or better the GUI reaches certainly a point of speed, where human interaction fails to feel the difference - just start a raytracer and compare it to a native implementation (eg old version of povray) or encode some mpegs or whatever - or maybe more crucial: try to browse the web! (other than this nice site) |
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25 May 2018, 20:00 | #591 | ||
son of 68k
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Some Amiga C compilers are way faster than VS on the pc. Merely booting the machine is also faster. And switching it off - it's simply different worlds. Play Protracker module - 0% cpu use. Decode Flac (with my program) - 90x real time (i believe it's enough ?). So yes, AOS is fast. It's just running on underpowered hardware. Changing the OS because the hardware is slow or the emulation isn't giving close to native speeds, is throwing the baby with the bathwater. |
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25 May 2018, 20:22 | #592 | ||||||
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and what does that tell us about the OS? nothing - we can only state that the chipset works as intended and/or uae is doing a good job in emulation the chipset. Quote:
the argument "fast enough" is like "nobody will need more than 640k RAM". Yes: for this specific use-case it is enough. And now i want to watch my latest 4k video. Quote:
Still: native code always wins. As for the "perfect ISA": Ideal would be a instruction set or at least a code, that contains extensive hints. E.g. what branch is more like to be taken - the importance of a loop, or in general what a section of code is meant to do. the holy grail, would certainly be an instruction set, that allows for binary translation being done ahead of time. Last edited by Gorf; 25 May 2018 at 21:10. |
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25 May 2018, 20:40 | #593 |
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Worse, this is Amiga, the computer for the creative mind - you want to edit that 4k video.
(Ironically I am posting this from an Intel NUC running DragonFlyBSD and FS-UAE /OS3.9, since attempts at AROS hosted on DFBSD still fail) |
25 May 2018, 21:02 | #594 | |
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Yeah right with an i7 in there!! The only thing related to Amiga is the name and the article even states this! Commodore USA they really did try! They kind of remind me of Commodore UK, they held on and ariston too! Check out those asking prices!! WHOA!! https://www.techradar.com/news/pc/co...-years-1072954 |
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25 May 2018, 21:36 | #595 | ||||||||
son of 68k
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Believe me, VS2015 that i have here is very slow. Quote:
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What do you mean, real or use ? Quote:
However it says the chipset can do things that are not that obvious on other "superior" machines... Probably not 500x, no. Quote:
It is enough for many use cases already. Sorry, for now i can only do the sound out of an mp4. Pretty sure it can be done if given a direct access to the host's gpu, though. But wait... can your RasPi do 4k video ? Quote:
Not always, no. Native code can be compiled in inefficent languages or use very poor algorithms so that emulated code ends up faster. Quote:
But it's not ideal as it is specific to some particular host and it might be more efficient to compute that data at runtime and cache it. Branches don't need this - a good host cpu has a good branch predictor that will do the job. Nah. Just execute any loop as fast as possible Do you think a computer can understand what it does ? That would require more than what the best AI can currently do. (Or your sentence had a different sense than it seemed to have.) Quote:
By all means, do not tailor the instruction set for a specific implementation ! |
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25 May 2018, 21:54 | #596 | ||||
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yes but only in 15Hz ... but thats looks great on a very slow movie
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(And no: I have not the slightest clue how to do this - apparently nobody does.) Last edited by Gorf; 25 May 2018 at 23:22. |
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26 May 2018, 09:28 | #597 | |||
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Hints in the code also take space, btw. Encoding space is valuable and there are better uses for it. Quote:
What information ? This is wholly unclear. Quote:
If one day we get a nice asic, these emulation hints will look ridiculously useless. I've said that somewhere before, but don't forget that architectures persist longer than implementations. Hints given to some machine to build some program are called code. Thus "enough hints" is like performing the conversion yourself. |
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31 May 2018, 16:07 | #598 | |||||
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Because it doesn't make any difference.
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NE = execute on Not Equal = Z condition code clear No S = doesn't set flags R0, R1, R2 ASR R3 ; R0 = R1 op (R2 ASR R3) Quote:
BEQ .skip ASR.L D3, D2 ; D2 = D2 ASR D3 NOT.L D2 ; ... AND.L D1, D2 ; D2 = D2 AND D1 .skip Note that I selected this instruction to illustrate a point. One 32 bit RISC type instruction doing the work of 4 68k instructions 64 bit in total. While being easier to decode, faster to execute and not overwriting potentially useful data. Quote:
The hardware costs for this is slim, each instruction would set the condition codes anyway, comparing condition codes against a specific condition is trivial and the ALU would only need to give the result to the branch unit. The complication in the decoder is how to extract the condition field and detect (and extract) the branch address. Trivial. Sadly the semantics of DBcc makes it hard to do in one standard instruction but op+branch still makes it easier to translate. Quote:
Not being able to do something like: ADD R0, R1, #1 LSL R1 Is also sad. That most instructions waste 4 bits is insane, that the PC is a general register a problem, that it only have 15 normal registers another. Quote:
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31 May 2018, 16:52 | #599 | |||||
son of 68k
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What difference would you want to make then ?
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(This is a general statement ; instructions doing several unrelated things together make code harder to read.) Quote:
When i wrote "for what", i asked for a concrete case. One can easily invent an instruction that does the job of many others, but if no program ever has these instruction sequences then it's pointless. And that is more or less the case here. Something like 90% of instructions in a typical ARM stream start with "E" (for "always true" condition) and not 10% will use the barrel shifter (i'm giving these from memory, if you think it's wrong then you may just disassemble code and make your own statistics). In fact it's similar to the use of branch and shift instructions in any other architecture. An example you could give is a real life routine, not just "clear a bitfield if some val is negative" (which btw is doable in 3 instructions in 68k rather than 4, but still not very useful). How many instructions, for example, to read a decimal number from a stream ? Quote:
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First thing to get is a complete instruction set encoding reference table and so far i've been unable to merely find that. It seems every model has own instruction set and it doesn't help. Quote:
RISC was an advantage in the past as it could implement relative costly methods for executing instructions fast (things like OoO, etc) but now there is a wealth of transistors and they have no advantage left. This is why ARM is beaten in performance by x86. This is also why IBM had to use exceedingly aggressive designs for POWER8 to still be able to compete (and it does only in floating-point). If you have to execute more instructions for doing the same job, today it's not possible to be faster. As simple as that. |
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03 June 2018, 22:17 | #600 |
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So why are there so few x86 phones around?
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