Address register indirect, word vs long

[deimos]

The one bit of code I have where the performance matters the most has at the heart of it a move.w instruction where I need to choose a destination addressing mode of (An, Dn.w) or (An, Dn.l).

If I chose the former I can't use interleaved bitmaps, if I chose the latter I can. If I chose to mix in bits of blitter stuff then interleaved bitmaps make so much more sense (just normal blits, not line drawing or filling), but I need to understand the cost.

I can make an estimate of how many times this characteristic move instruction will get called per frame, but how do I go from information like this that I found online:

d(An,ix)	Address register indirect, index	10(2/0)	14(3/0)

to an actual human relatable number?

[hooverphonique]

The size of the index register doesn't matter regarding cycles.

[roondar]

The numbers you mention seem wrong, a move from d(an,ix) is never as low as 10 cycles. For reference, I use this site for my CPU timing info: http://oldwww.nvg.ntnu.no/amiga/MC68...000timing.HTML

Anyway, the numbers in parentheses show the number of memory read/write cycles/actions the instruction causes on the bus, the number in front of the parentheses shows the number of cycles the instruction takes.

If we look at move.w d(an,ix) on the site I linked above, we see that the instruction costs a minimum of 14 cycles (when moving a word from d(an,ix) to dx) and a maximum of 26 cycles (when moving a word from d(an,ix) to an absolute long address). For longs we can see it is between 18 cycles (when moving a long from d(an,ix) to dx) and a maximum of 34 cycles (when moving a long from d(an,ix) to an absolute long address).

Then simply compare this to the speed of the CPU, which does about 7 million cycles per second/140.000 cycles per PAL frame.

In short, using words can be quite a bit faster - but if depending on the opcode, the difference can be fairly small.

Edit: I misread your post, I thought you wanted to know the difference in speed between move.w <blah> and move.l <blah>. Ignore what I said, hooverphonique is correct.

[deimos]

Originally Posted by hooverphonique

The size of the index register doesn't matter regarding cycles.

I see. I was misreading - word vs long is the size of the data being written. In that case I need to go back and look at what I've done.

[deimos]

Originally Posted by roondar

The numbers you mention seem wrong, a move from d(an,ix) is never as low as 10 cycles. For reference, I use this site for my CPU timing info: http://oldwww.nvg.ntnu.no/amiga/MC68...000timing.HTML

Anyway, the numbers in parentheses show the number of memory read/write cycles/actions the instruction causes on the bus, the number in front of the parentheses shows the number of cycles the instruction takes.

...

Then simply compare this to the speed of the CPU, which does about 7 million cycles per second/140.000 cycles per PAL frame.

Thank you, that site looks to have all the data and even explains it, and says, as hooverphonique did, "The size of the index register (ix) does not affect execution time".