About DRAM

[alexh]

(Separated from a Thread discussing why you cannot use 64 MByte SIMMS on Apollo 1260's and must add a 2nd SIMM socket and use 2x 32Mbyte ones)

Now please bare with me as I know nada about DRAM or SIMMS etc. in my work we only ever use SRAM (unless your the memory controller guy which I am not). SRAM is very easy to understand as they behave just like linear arrays in C.

Question : What is so different between 2x SIMMS and one SIMM 2x size that they are not easily interchangeable?

If it were a single SRAM the CE (chip enable) for the second SIMM could just be moved to become the MSB for the address.

I would guess that since a SIMM is DRAM and not a single chip but multiple devices with each chip not having a linear address but using ROW & COLUMN + then we have PAGEs etc. I guess 2x size SIMM needs more address lines (and some sort of en/decoder) whereas 2x SIMMS just require additional CE lines? Any idea exactly what?

The answer will be more technical and complicated and will no doubt involve words like PAGES, CE, ROW, COLUMN, DENSITY, RAS, CAS etc. but I'd appreciate a REAL technical answer not a guess, or a dumbed down summary. Ta very much.

[Jope]

Let's discuss this in a separate thread.

Even though you specifically asked not to give links like this, here's a superficial link for you.

http://arstechnica.com/paedia/r/ram_...e.part1-4.html

[Zetr0]

@jope

thats a good link indeed =D