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Old 11 April 2017, 21:31   #21
ross
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Originally Posted by Wrangler View Post
@ross: Hi - just tested both of those adfs on a real A500 (OCS) and they both work fine, no glitches.
Thanks!

Bye,
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Old 19 April 2017, 18:17   #22
losso
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Same on ECS Agnus here with ross' versions.

I have started to build a minimal example to reproduce this and tried to rule out other factors one-by-one: the copperlist was unbuffered, waiting until mid-screen before the blit queue, double-checking interrupt handler, check if I introduced a bug into the framework etc. -- so far with no success.

Since I have brought back some other fails-on-hardware bugs to fix from Revision (probably unrelated, though), it might take some time until I can get back to this.

Thanks for all your efforts on pinning this down so far!
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Old 20 April 2017, 08:47   #23
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Same on ECS Agnus here with ross' versions.

I have started to build a minimal example to reproduce this and tried to rule out other factors one-by-one: the copperlist was unbuffered, waiting until mid-screen before the blit queue, double-checking interrupt handler, check if I introduced a bug into the framework etc. -- so far with no success.

Since I have brought back some other fails-on-hardware bugs to fix from Revision (probably unrelated, though), it might take some time until I can get back to this.

Thanks for all your efforts on pinning this down so far!
I've just fixed some nasty fails on real hardware bugs in a game I'm working on. Maybe we should start a thread to document the pitfalls as we find them to help people avoid our mistakes in the future.
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Old 20 April 2017, 09:31   #24
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I've just fixed some nasty fails on real hardware bugs in a game I'm working on. Maybe we should start a thread to document the pitfalls as we find them to help people avoid our mistakes in the future.
Take me as interested
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Old 20 April 2017, 10:09   #25
Toni Wilen
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Only if test program exists that confirms it. It must not be some boring theory without proof (seen those too many times..) or "just to be safe, do this"
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Old 20 April 2017, 11:19   #26
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Only if test program exists that confirms it. It must not be some boring theory without proof (seen those too many times..) or "just to be safe, do this"
I'm my case they were just bugs that for whatever reason didnt manifest ever under emulation.

For example I was poking the bitplane pointers in a copper list in a non synchronised way which I'm guessing meant that every now and then on real hardware left them in an invalid state when they were latched?

Timing on real hardware was everything, an unrelated change would change the timing and mask the bug.

In the end I disabled th copper DMA before patching and that seemed to fix it.
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Old 20 April 2017, 11:28   #27
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You probably hit the chipset feature where write to DMA pointer register does nothing if next cycle is same DMA channel's data read/write cycle. (Most emulation modes do not emulate this because wrong CPU timing, especially if not 68000, can break situations which work in real hardware)

This is why real world test case is needed. To find and confirm the exact root cause and to test if it is hardware revision specific.
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Old 20 April 2017, 11:33   #28
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You probably hit the chipset feature where write to DMA pointer register does nothing if next cycle is same DMA channel's data read/write cycle. (Most emulation modes do not emulate this because wrong CPU timing, especially if not 68000, can break situations which work in real hardware)

This is why real world test case is needed. To find and confirm the exact root cause and to test if it is hardware revision specific.
I can try and check out an old version of my game that had this bug. Problem is, the bad effect was very intermittent, but I was able to reproduce it on an a500 and a1200.

I had a blitter issue that was 100% reproducible on real hardware and perfect under emulation so I can try and resurrect that if you're interested.
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Old 20 April 2017, 13:40   #29
Toni Wilen
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I can try and check out an old version of my game that had this bug. Problem is, the bad effect was very intermittent, but I was able to reproduce it on an a500 and a1200.
These are annoying but if it happens in real a500: try to create simple test case (does not need to be really simple but all "useless extra" removed)

Quote:
I had a blitter issue that was 100% reproducible on real hardware and perfect under emulation so I can try and resurrect that if you're interested.
Yes please, this is the only way to document and emulate these properly. (Unless it is writing to BLTCON0/1 after blitter has been started..)
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Old 21 April 2017, 09:25   #30
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These are annoying but if it happens in real a500: try to create simple test case (does not need to be really simple but all "useless extra" removed)



Yes please, this is the only way to document and emulate these properly. (Unless it is writing to BLTCON0/1 after blitter has been started..)
I emailed you the buggy version of the game.
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Old 23 April 2017, 15:00   #31
Toni Wilen
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I had a blitter issue that was 100% reproducible on real hardware and perfect under emulation so I can try and resurrect that if you're interested.
Fixed.

Blitter ADAT and BDAT (BDAT in this program) writes in non-DMA mode didn't shift in old value (if shift was non-zero). Old data from last blit corrupted the font writer's mask data. No corruption if old data was zero.

Previous blit used B-channel, next blit had B-channel disabled but it was part of used minterm, BLTBDAT was properly set by CPU write but if shift was non-zero, old data was shifted in to final "B hold" value.

It seems "old" data ("A old" and "B old" in HRM) is automatically cleared only if channel is enabled when writing to BLTSIZE.

EDIT: Only B channel "remembers" old value. "A old" is always cleared.

Last edited by Toni Wilen; 24 April 2017 at 17:52.
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