Question for the pros about blitter clear and triple buffering

[mc6809e]

I've noticed in serveral ST ports to the Amiga that often the blitter is used to help clear memory, though ironically this can actually make things slower than MOVEM.L when done naively, the problem being the idle cycles, which have to be taken even when other DMA is occuring. A clearing blit done during four bitplane display DMA fetch will cause the blitter to write on every fourth cycle during the clear, slower than MOVEM.L.

I can imagine a programmer thinking, "this one simple case is easy for the port -- I'll try it" and being disappointed that it's slower than just using the CPU.

I think Starglider is an example of using a blitter clear naively.

Obvious solution is to start with a displayed framebuffer, a buffer being cleared with the blitter, and a third buffer where the new image is begin built (by the CPU in the case of a simple ST port).

Seems like a missed opportunity for an easy gain in speed.

Too complicated for a port? Not enough spare memory? Not used because of a misunderstanding about how the blitter works?

[Samurai_Crow]

It depends on whether you have real fast RAM or not. The blitter doesn't block the CPU if you have fast RAM. They operate in parallel.

Also, it depends on if you have AGA because 32 bit writes are allowed on AGA but not if you have ECS or OCS. The 16 bit chipsets have 16 bit chip RAM so a long write takes 2 bus cycles each.

[chb]

AFAIU the workings of blitter idle cycles were largely undocumented, they appear in some early errata to the HRM, but the later eiditons of the HRM seems to omit them completely:
http://amigadev.elowar.com/read/ADCD.../node0127.html

The HRM, while being an excellent documentation, contains some false information that persisted quite a bit and may have mislead programmers to write non-optimal code, e.g. the statement that the 68000 can only use the even-numbered memory cycles.

And then of course no one bothered when porting from the ST.