Terrible Fire Accelerators

[8 Bit Dreams]

Originally Posted by Xicorpt

Thanks, will try the 10ns first. As soon as the cpld's arrives I will post my findings....

Wishes of speedy recovery to plasmab !

About memory:
I think it's good idea - to try different memory chips filtering all parts and prevent other persons doing same mistakes we did..
For now (40Mhz CPU, 50Mhz firmware):
Alliance 15ns chips - working good (7600 Dhrystones)
Alliance 12TIN - working good (9040 Dhrystones)
ISSI -? No info atm

About cpld's:
Have swapped cpld's to 10ns by using hot air soldering station, however, it's a bit tricky with one chip, as FPU Socket is on the way, so You can't use knife soldering tip to reflow the pins after that..

waiting for TF534 wanna run SATA on Amiga

[mattymuc]

Originally Posted by 8 Bit Dreams

waiting for TF534 wanna run SATA on Amiga

Yeah, and 4MB RAM :-) Awesome!

[kim_jorgensen]

Originally Posted by 8 Bit Dreams

Alliance 15ns chips - working good (7600 Dhrystones)
Alliance 12TIN - working good (9040 Dhrystones)

Is this with the same firmware?
I thought that is was the CPLD alone that controlled the bus timing.

[8 Bit Dreams]

Originally Posted by kim_jorgensen

Is this with the same firmware?
I thought that is was the CPLD alone that controlled the bus timing.

Yes, same 50Mhz firmware, different speed because of timing of the chips: 12ns vs 15ns makes this difference.
Now i am starting to understand the answer on my question on the stream about 45ns RAM IC's. These will have 4Mb of RAM, but will de three times slower than 15ns..

@dragmar
just check this thread - all links to firmwares are present here, i do not own any "special" firmware.
Also check Your Xilinx chip, there are two types of them: 7x and 10x, 7x will NOT working correctly! (i got 24x of them atm, have bought them on Ebay, there was sticker on them that covered that line, (these was already flashed), have populated two boards, both are not working on 40/50Mhz with FPU installed, showing only 7Mhz, however, when i remove FPU it kinda works, but i am unable to run any software.
It seems that there are more persons who own "wrong" cpld's, i wish i was able to help, all we need - is to correct the timings and recompile the firmware, unfortunately i have no idea how to do it as i have nothing to do with programming or soldering in my job - it's just my hobby. I will try to get help later from some person that have a clue how it is doable, or maybe Stephen will find some mojo to do this if we all start to cry ang begging him will see..
Atm is better to watch out, and avoid 7ns CPLD's and 68881 FPU's.
About 68882:
it is not so transparent:
i have bought a lot of five FPU's from this seller:
http://www.ebay.de/itm/5pcs-MC68882F...L/251245225321
Production stamp say's: 1C12R none of these five is working! Getting light yellow or black screen with them. Got refunded today.
However, i got another 3x pieces from other seller WITH THE SAME time stamp: two chips worked right out of the package, third had corroded pins, this IC started to work after cleaning.
hope it is usefull info for some of You
kind regards,
Viktor

[plasmab]

Originally Posted by kim_jorgensen

Is this with the same firmware?

I thought that is was the CPLD alone that controlled the bus timing.

Me too? V confused.


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[8 Bit Dreams]

Originally Posted by plasmab

Me too? V confused.


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i have no other explanations to this, except 12ns vs 15ns timings:
http://eab.abime.net/showpost.php?p=...postcount=1783
http://eab.abime.net/showpost.php?p=...postcount=1817
both cards have 48.40Mhz frequency and same firmware, however, different memory chips

[Stedy]

Originally Posted by plasmab

Me too? V confused.


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Am I missing something but after re-building the TF530 design from the Github sources and doing a post layout timing analysis, I get errors, see attached.

Have you tweaked anything in the UCF files for the JED files you supply for different speed bins?

BTW, using faster -7 CPLDs should not matter, you can always go to a faster grade, never a slower one as the part number details the maximum speed, which this design should not hit.

[Tachyon]

Reason 103 I don't use lead free solder. ;')

https://nepp.nasa.gov/whisker/photos/index.html

[8 Bit Dreams]

Originally Posted by Stedy

Am I missing something but after re-building the TF530 design from the Github sources and doing a post layout timing analysis, I get errors, see attached.

Have you tweaked anything in the UCF files for the JED files you supply for different speed bins?

BTW, using faster -7 CPLDs should not matter, you can always go to a faster grade, never a slower one as the part number details the maximum speed, which this design should not hit.

In my case 7ns cpld's isn't working of fully populated board. Withiut FPU it kinda works, however, i can not run any programs/games

[plasmab]

Originally Posted by Stedy

Am I missing something but after re-building the TF530 design from the Github sources and doing a post layout timing analysis, I get errors, see attached.



Have you tweaked anything in the UCF files for the JED files you supply for different speed bins?



BTW, using faster -7 CPLDs should not matter, you can always go to a faster grade, never a slower one as the part number details the maximum speed, which this design should not hit.

Nope. I just specked the clock timings. I ramped them up as the clocks go up. The 530 source on GitHub is old.

Virtually everything in the design is synced off clock edges so I'm confused.

I call BS on the speed differences with different RAM speeds because the RAM doesn't have anything whatsoever to do with the timing acknowledge. That's completely fixed by the CPLD. I could believe that you may be able to run faster clocks but you haven't done the test you think you have if try different ram speeds and get different answers. Repeat the test 20 times for each and take an average and I bet you get the same.




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[oggie]

Originally Posted by plasmab

Nope. I just specked the clock timings. I ramped them up as the clocks go up. The 530 source on GitHub is old.

Virtually everything in the design is synced off clock edges so I'm confused.

I call BS on the speed differences with different RAM speeds because the RAM doesn't have anything whatsoever to do with the timing acknowledge. That's completely fixed by the CPLD. I could believe that you may be able to run faster clocks but you haven't done the test you think you have if try different ram speeds and get different answers. Repeat the test 20 times for each and take an average and I bet you get the same.




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If the source on github is old, are you planning on updating it? How do we get the most recent? Search this thread?

Thanks

[plasmab]

The jeds are up to date. The actions of various folk rerouting my boards has made me rethink my open source policy.

Essentially I would be happy with someone deriving a new product that adds value .. but a "look at me.. I can make a board and pretend I designed it" annoys me enough that I'm making people comprehend the HDL side of things to hit 50Mhz. Not just recompile my work and pretend they did it

The core is there if you want to derive and the jeds are there if you want to manufacture. But if you want your own design you'll need to understand it all


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[Chucky]

I understand what you are saying.. but hey.. most of us now know that this stuff is yours.. and they are just morons..

[Xicorpt]

Originally Posted by Tachyon

Reason 103 I don't use lead free solder. ;')

https://nepp.nasa.gov/whisker/photos/index.html

Mind blowing, will have that in mind for my next doomsday device ....

[8 Bit Dreams]

@Stephen:
As far i know - only Keeper2k has rerouted Your board making 4 layered one..
Did You tried ISSI memory on Rev.3? I didn't understood what do You mean, saying this board doesn't work on the last stream..No memory detected? CPU isn't booting?

[plasmab]

Originally Posted by 8 Bit Dreams

@Stephen:
As far i know - only Keeper2k has rerouted Your board making 4 layered one..
Did You tried ISSI memory on Rev.3? I didn't understood what do You mean, saying this board doesn't work on the last stream..No memory detected? CPU isn't booting?

Others have rerouted the TF530. They've taken copyright notices off too. But if they've changed the CPLD pinouts they're stuck at 20Mhz and if they haven't I can force them to open their sources.

I started to build a Rev 3 but I think I fried the clock circuit or I've got a short somewhere. CPU isn't starting... haven't had time to debug.


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[Black68]

Originally Posted by Mr.Flibble

Just a quick update, I built up one of the relocator boards - it's a touch tricky soldering around the socket overlap, but do-able with plenty of flux and going sparingly with the solder.

You might need to bend/resolder the cap at C816 otherwise it'll stop the board going into the cpu socket properly, but clearance looks good up to the big caps at the top of the board.

Just going to check clearance for closing the case now...

Edit: Looks good - keyboard is well clear, no issues closing the case - pics to follow.

Edit 2: Pics attached.

Would it be possible to buy one riser PCB from yours? Thanks in advance!

[Mr.Flibble]

Originally Posted by Black68

Would it be possible to buy one riser PCB from yours? Thanks in advance!

You can either order them from Easy EDA (https://easyeda.com/order) using the Gerber files on my github, or you can order them via DirtyPCB's from the following link:
http://dirtypcbs.com/store/designer/...-gerbers-1-zip

At the moment, Easy EDA is far cheaper at $2 + postage, but DirtyPCBs you can just order from and not worry about the gerbers/setup etc.

[8 Bit Dreams]

Hi,
I have some Mr.Flibble's relocator pcb's left. Also some ready built
Also ready built TF530 running @50Mhz
Postage 4€ as surface mail or 6.50€ tracked and insured anywhere in the world

[plasmab]

All: I have just (finally) submitted the TF534S to the boardhouse..

Sata + 4Mb + Z3 version of the 530.