29 January 2020, 19:59 | #1 |
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Using the disk DMA to clear memory?
Is this possible? Saw this mentioned in a FB thread... anyone done this?
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29 January 2020, 20:48 | #2 |
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29 January 2020, 21:30 | #3 |
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Someone said they had used it, and it had help save some cycles...
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29 January 2020, 21:54 | #4 |
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Let's do two calculations: you can clear 1878byte/frame, so for a simple 320x256 single plane you need 10240/1878=5,45 50Hz frames to do it.. With the blitter you need only few video lines for the same bitplane (using also the same DMA slots of the unused DISK DMA). I dont see any advantage. The only (negligible) use could be to clear small areas of memory in a deferred way from the blitter and the processor. Nothing striking. EDIT: anyway for a DISK DMA start you need a 'signal' from Paula and the MFM bit stuffing is at max 2ns/bit, so this 'virtual' figure is smaller.. all this for me has no logical use (even if it were possible) Last edited by ross; 29 January 2020 at 22:28. |
30 January 2020, 04:41 | #5 |
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When clearing, using one channel only, the blitter cannot write during every available DMA slot. In the same way that you can clear memory on the 68000 more quickly by using the blitter and CPU simultaneously, couldn't you use the disk DMA and blitter simultaneously, accelerating the clear with the disk DMA slightly?
I'm not sure how you'd make the disk DMA write the desired data though. |
30 January 2020, 06:18 | #6 |
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30 January 2020, 06:44 | #7 | |
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Quote:
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30 January 2020, 07:30 | #8 | |
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So it makes no sense to use the DISK DMA, in any case its allocated DMA slot cycles would be used by the blitter. |
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30 January 2020, 09:02 | #9 |
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30 January 2020, 09:39 | #10 | |
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By writing to DSKDAT maybe ? |
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30 January 2020, 10:18 | #11 | |
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Yes that blitter can slow down the CPU, but it can use every free cycle (as the CPU), that in this specific case could be also DISK DMA cycles. So these cycles "allocated regardless if they are used or not" are usable/used by the blitter/CPU during the clear operation As I've written, the only (negligible) use could be to clear small areas of memory in a deferred way from the blitter and the processor (but not 'instead'). Last edited by ross; 30 January 2020 at 12:38. Reason: added CPU/blitter pair, not only blitter |
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30 January 2020, 10:46 | #12 |
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If audio or disk or any DMA slot is not used by higher priority Agnus DMA channel, it is always usable by blitter or CPU (if blitter or CPU needs it).
Allocation is dynamic, unused DMA slots are never unavailable for blitter or CPU. |
30 January 2020, 11:22 | #13 |
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Toni is totally right here
Last edited by ross; 30 January 2020 at 12:35. Reason: master Toni :D |
30 January 2020, 11:28 | #14 | |
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But if there are free disk/audio "slots" then surely both the CPU and Blitter could access them? Edit: assuming the CPU manages to get aligned to the correct slots to do so, obviously. It'll still only access memory every other cycle at best. *) that is, not cycles during which disk/audio DMA are running but idle, but cycles where disk or audio DMA actually needs to access memory for that particular slot. Last edited by roondar; 30 January 2020 at 11:38. |
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30 January 2020, 11:44 | #15 | ||
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EDIT: anyway this is not simple, i think only on AGA you can 'overrun' bitplane DMA up to DISK/AUDIO slots but sure OCS/ECS for refresh slots. Quote:
Last edited by ross; 30 January 2020 at 12:53. |
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30 January 2020, 11:57 | #16 | |
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If the CPU gets "misaligned" somehow at the start of a scanline, it will use all the AUDIO/DISK DMA channels slots (and sprite, etc) that are available until it's forced back into alignment. It definitely won't make much of a practical difference and often such misalignment is very temporary, but it's certainly theoretically possible for the CPU to be so aligned for all of those cycles in a scanline. If this understanding is wrong, well, I'd love to learn ----- On the topic of clearing with disk DMA and it's usefulness: thinking about this a bit more, I can see a "kind of, maybe" use-case here. Now, this definitely won't improve performance, but might still be useful in some scenarios. You could effectively use this as a sort of "fire-and-forget" memory clear that just does it's thing while rest of the code gets run for the frame. So for instance, you could call disk DMA to clear a small section of memory you need to use next frame, while the rest of the code goes on doing other stuff with the Blitter or CPU. Not sure how useful this is, but it's still perhaps interesting. |
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30 January 2020, 12:32 | #17 | ||
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EDIT: I'll edit my previous message adding CPU more than blitter access possibility on these DMA slots (Toni is always right ) Quote:
Last edited by ross; 30 January 2020 at 13:01. |
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30 January 2020, 14:02 | #18 | |
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There are also instructions that have non 4 divisible cycle counts and long instructions like MUL and DIV. |
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30 January 2020, 14:57 | #19 | |
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I've written a little test prog with unrolled movem series interleaved by a 6 cycles lsr d0,d0 (d0=0) and in VisualDMA debugger the effect is pretty visible. |
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30 January 2020, 16:47 | #20 |
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This post asks:
Can you clear memory using disk DMA? Which is a fascinating question to me because it's not one I heard before. Assuming it's possible, the implicit follow up question is: Is there a situation that is useful or gives some benefit? I can think of a situation in which it could be a performance enhancement and not just a curiosity. I tried to allude to this before, but didn't explain it very well (or really at all) so let me try again: Let's say you have the following situation: - CPU is not using the chip RAM bus much, or at all (doing expensive internal operations or running out of fastram) - you want to clear a buffer If you use the Blitter, in D channel mode as normal, you cannot utilize every chipram access cycle due to how the blitter works, so your bus access looks like: Code:
-B-B-B-B-B-B-B-B-B-B-B-B... - = Idle B = Blitter Code:
-D-D-D-------------... - = Idle D = Disk Code:
-DBDBDB-B-B-B-B-B-B-B-B-... - = Idle B = Blitter D = Disk If I'm right about this behavior, you now have ~1.8 KiB of extra clearing bandwidth per frame. Naturally you could replace the blitter clear operation with some other operation that also cannot saturate the bus as well (like an A->D copy of for example) and similarly be able to utilize some extra chip ram access slots. I could be wrong about the timing, or the effect the contention would have on delaying the blitter. It could be proven either way with a small piece of test code, but I bet Toni also just knows |
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