Roomboot question(s)

[Asman]

on the http://wandel.ca/homepage/execdis/exec_disassembly.txt I found followin code which I don't understand

        ; Set up port A on the first CIA (8520-A).

FC00FE  move.b    #3,BFE201         Set low two bits for output. (ciaa pra)
FC0106  move.b    #2,BFE001         Set boot ROM off, power light dim. (ciaa ddra)

Why I must set up port A on the first CIA ?
As I checked even with first line my tiny custom roomboot (which only copy code to ram and run it and set screen to some color) works fine. Is this mean that second line is not necessary ?
I'm not sure but I don't find any information that set bit 1 in ciaa ddra makes boot Rom off. Am I wrong ? Can someone explain it a bit more. Thanks a lot.

[Toni Wilen]

Which Amiga model? Gayle based systems switch off overlay when first CIA (any CIA register, any CIA) is done.

[Asman]

Thanks for answer.
I didn't know that depend from Amiga model ? My knowledge about it is weak. Where I can find more information about it ?

[Toni Wilen]

It was mentioned in Gayle datasheet and I am sure it was found earlier because it is easy to notice that CIA OVL pin does nothing on Gayle based Amigas and schematics shows CIA OVL pin is not connected. (It is re-used as a CD audio mute pin on CD32! I think I originally found out how it worked when I started doing CD32 emulation)

http://eab.abime.net/showpost.php?p=399851&postcount=1

The ROMs are also selected in the range from $0000000 to $OlFFFFF when the internal overlay signal (OVL) is high (this allows the RESET vectors to be contained in the ROMs). The internal OVL signal becomes asserted at reset, and negates on the first write to CIA1 (address range of $BFDOOO to $BFDFFF.

(and I remembered wrong, it was CIA-A only, not both)

[Asman]

Thank a lot Toni for answers. I'm back with next bunch of questions

FC00D2  lea       040000,SP         Set stack pointer to top of first 128K.
FC00D8  move.l    #$020000,D0
FC00DE  subq.l    #1,D0             Delay loop.
FC00E0  bgt.s     FC00DE

In above code stack pointer is set. Ok, but the question is (perhaps stupid) where point SP before was set ?

For what is used delay loop which is cpu depend ?

[Toni Wilen]

Originally Posted by Asman

In above code stack pointer is set. Ok, but the question is (perhaps stupid) where point SP before was set ?

680x0 fetches both PC and SP from memory after hardware reset.

Address 0.L = initial SP (ROM identifier and JMP opcode normally in Amigas, boot code needs to set correct SP)
Address 4.L = initial PC

For what is used delay loop which is cpu depend ?

I guess (originally?) it was added to allow some slow hardware to finish reset processing before rom code tries to initialize them or something like that.

[Asman]

I'm back again with bunch of questions. I'm trying to do custom romboot but now I have problem with ints. Mean they don't work. I set for example VERTB int in following way.

		move.w	#$20,intena(a5)
		move.w	#$20,intreq(a5)

		lea	irq(pc),a0
		move.l	a0,$6c
		
		move.w	#$c020,intena(a5)

;... rest code

irq:		movem.l	d0-a6,-(sp)
		lea	_custom,a0

		move.w	intreqr(a0),d0
		and.w	#$20,d0
		beq	.end

		move.w	#$505,color(a0)

.end
		move.w	#$20,intreq(a0)
		nop
		movem.l	(sp)+,d0-a6
		rte

And of course color of background never change. I set breakpoint into label irq but debugger never break on it. There is something which I missing ?

Edit: a5 = $dff000, dma is enabled ($380).

[hooverphonique]

did you turn off the rom overlay? otherwise I suspect changing the level 3 vector ($6C) doesn't work.

[Asman]

Yes, I did that on begining of the code right after delay loop

	;first access to cia-a switch off overlay (Gayle based systems)
		move.b	#3,_ciaa+ciaddra
		move.b	#2,_ciaa

[phx]

Did you set the CPU's interrupt mask in the SR register accordingly?
Did you enable the display, so that a VERTB interrupt may happen?

[Toni Wilen]

Most likely reason is too high interrupt mask in SR register. (Vertical blank does not need any special initialization)

Getting hardware in sane state after powerup/reset is not that simple

[Asman]

Originally Posted by phx

Did you set the CPU's interrupt mask in the SR register accordingly?
Did you enable the display, so that a VERTB interrupt may happen?

eh... I see that my knowledge about 68000 is a bit weak, I didn't know that (SR register contains int mask). When I added

move.w #$2200,sr

then my test with vertb int pass. thanks a lot. And I see that must learn more about 680x0.

@Toni

Getting hardware in sane state after powerup/reset is not that simple

Indeed