07 April 2024, 11:59 | #3461 | |
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A stock A1200 CPU (without Fast RAM) and an SNES CPU have similar MIPS. Chip RAM only A1200 with packed chunky support would be similar to SNES. 1 MB Fast RAM equipped A1200 would be nearly twice the MIPS over SNES's CPU. A1200 with 1 MB Fast RAM + 2 MB Chip RAM baseline could allow 386DX with 4 MB RAM and 3DO with 3 MB RAM profile game ports. A1200 with 1 MB Fast RAM + 2 MB Chip RAM baseline is the "foot in the door" configuration which enables the existing Budgie's 32-bit Fast RAM controller. Last edited by hammer; 07 April 2024 at 13:54. |
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07 April 2024, 12:20 | #3462 | |||
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SNES does NOT deliver gaming PC's "new 32-bit 2.5D/3D gaming experience". SNES delivers a strong late 16-bit 2D gaming experience. Quote:
[ Show youtube player ] Ultima Underworld The Stygian Abyss on 80386 @ 25MHz I had a 386DX-33/ET4000AX-based PC and A3000/030 @ 25Mhz. PC has VGA while the Amiga/Atari ST version is like improved EGA graphics. Quote:
I run Legends of Valor on a faster A3000 @ 25 Mhz which is like running Wing Commander with 16 colors. Last edited by hammer; 07 April 2024 at 14:11. |
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07 April 2024, 13:39 | #3463 | |
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Back at you. Amiga OCS already reached 6-bitplanes with a 5-bit (32) color register hack known as EHB. Sega looked into the gaming market and decided on a fast 64-color bitmapped for the Mega Drive's 1988 release. Commodore is happy to dismantle the original Los Gatos Amiga group. Nintendo looked into the gaming market and decided on a fast 256-color bitmapped for the SNES's 1990 release. Meanwhile, the SVGA cloners have cost-reduced IBM VGA/8514 standards. Commodore had zero response to SNES until Q4 1992 while SNES has reached an install base with critical size. Commodore shifted from being a leader to a follower i.e. Commodore looked at PC's 256 color standard. In the 1990s, there is no "Amiga tech jump" package for purchase which forced Commodore to improve its in-house tech with less management experience when compared to the competition. Your argument is a follower and not even zero-sum. Last edited by hammer; 07 April 2024 at 14:13. |
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07 April 2024, 17:15 | #3464 | |
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Come on... SNES cpu is weaker than a 68000. 020 with CHIP RAM only plays in another league. 020 with FAST RAM is miles away. |
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07 April 2024, 18:12 | #3465 | |
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Once you reach that point, making everything byte based starts to be an easier win on every level. And meaningful image quality improvements at that point start being much bigger jumps to 16-bit, 24-bit or 32-bit displays, all of which also work better without a planar arrangement. |
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07 April 2024, 18:16 | #3466 |
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Sure, but the SNES isn't as reliant on it's CPU. Having the ability to do things like rotate and scale the entire display, or do colour maths to create transparency/lighting effects in real time meant that it could pull off an awful lot of things that were hard to do with a purely CPU driven solution even with a high end CPU of the era.
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07 April 2024, 19:15 | #3467 |
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@AestheticDebris - sure, but neither is Amiga...
On the other hand 7MHz 68000 is already faster than 3.58MHz Ricoh 5A22 which is 16bit version of 6502 (but has 8 bit data bus and 2 address buses, one 24 bit and one 8bit but they do not combine into 32). Trying to say 14MHz fully 32bit (registers, execution units and ram interface) EC020 has similar performance is basically BS. On the other hand great many of SNES games uses SA1 coprocessor which is basically same 65C816 core but clocked around 10MHz so roughly 3x faster. Other games uses DSP based on NEC design, yet another games uses SuperFX chip which is 16bit RISC with clock over 20MHz. So that's how it goes. SNES was DELIBERATELY crippled at launch so Nintendo could sell enhancement chips and take more money. But the fact is - it did allow SNES to keep up for quite a while and with pretty great looking games like Donkey Kong Country. |
07 April 2024, 20:40 | #3468 | |
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There was a pretty detailed series of articles, mainly focused on the inefficiency of planar memory accesses: https://www.linkedin.com/posts/cesar..._campaign=copy Leaving HAM alone, let's imagine a 5 bit packed format. To "move" an object of 16x16 pixels (in 32 colours) on the screen using the blitter, you'd have to access 5*16x16 bits (16*5 = 80 one row x 16 rows). Depending on the "relative position" of the object in the packed grid, an extra word might be read (and later written) by the blitter for each line, whereas with planar graphics you'd have to do an extra access for each line for each of the bitplanes, most of the times (excluding the case when the object would be perfectly aligned to a 16 bit boundary). Again, increasing the complexity of the display fetching logic, it seems that packed graphics is always more efficient (bandwidth-wise) than planar, hence I wonder if it was chosen for a particular reason (cost of implementation with the tech of the time) or it's a bias due to other things. I am fairly sure the engineers had a very good reason to choose it, just wondering why and also why they didn't try to move in a different direction with AGA, adding proper packed (aka chunky) modes. |
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07 April 2024, 20:56 | #3469 | |
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A 5-bit packed format would be an absolute nightmare, imagine trying to plot an arbitrary pixel. Because 5 doesn't go into 16 cleanly it could start midway through a word and may or may not cross word boundaries. There's a reason machines with packed displays typically used 2, 4, 16 or 256 colour depths. Bitplanes are a lot easier for arbitrary depth values because alignment is never an issue. And things like blitting are simplified because it's the same operation, just done X times, rather than having to do slightly different work per pixel depth. Last edited by AestheticDebris; 07 April 2024 at 23:52. |
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07 April 2024, 21:08 | #3470 | |
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I think it's based on the initial idea of Jay Miner to create a platform able to run flight simulators. So the dual playfields mode, you can manage a foreground and a background without doing computations. And yeah, on one simulator, I forgot which one, the horizon was able to rotate very fast like in real jet fighter. |
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07 April 2024, 22:33 | #3471 | |
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Remember, the very first game with an enhancement chip was a delayed launch title, Pilot Wings! If it's a money gauging idea, i wouldn't go that far. But it did help significantly with making the low-power SNES base unit somewhat future proof. |
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08 April 2024, 00:53 | #3472 | |
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Ricoh 5A22 has multiplication and division registers which are missing in 65C816 CPU. Ricoh 5A22 additional circuitry for generating interrupts on calculated screen positions and generating non-maskable interrupts on V-blank. Unlike the stock wedge Amigas, SNES uses discrete memory pools for the CPU's system RAM and GPU's VRAM. Last edited by hammer; 08 April 2024 at 02:12. |
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08 April 2024, 01:06 | #3473 | |
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68000 has 16-bit ALU with 32-bit registers that are useful for 32-bit programming models for 32-bit desktop OS. SNES wasn't designed for 32-bit desktop OS and it was purpose-built for strong 2D games e.g. Ricoh 5A22 has custom hardware. Note why multimedia SIMD still has 8-bit and 16-bit datatypes for multimedia processing. In addition to the 65C816 CPU core, the 5A22 contains support hardware, including: Controller port interface circuits, including serial access to controller data An 8-bit parallel I/O port, which is mostly unused in the SNES Circuitry for generating non-maskable interrupts on V-blank Circuitry for generating interrupts on calculated screen positions A DMA unit, supporting two primary modes: General DMA, for block transfers at a rate of 2.68 MB/s H-blank DMA, for transferring small data sets at the end of each scanline outside of the active display period Multiplication and division registers Two separate address busses driving the 8-bit data bus: a 24-bit "Bus A" for general access, and an 8-bit "Bus B" mainly for APU and PPU registers. ------ SNES has discrete memory buses for the CPU's system RAM and GPU's VRAM. A500's 16-bit bus is shared between the CPU and GPU. Stock A1200's 32-bit bus is shared between the CPU and GPU. A1200 has a 32-bit Fast RAM controller built into Budgie with no RAM Chips. Commodore didn't see 6502's DDR potential e.g. AMD's K7 (data) 64-bit EV6 bus with DDR implementation. Alpha 21264 has a bidirectional 64-bit double data rate (DDR) data bus. MOS 65xx has some interesting tech. [ Show youtube player ] Starting at 11:42, SNES's Wolfenstein 3D with Ricoh 5A22 CPU doing most of the heavy lifting. [ Show youtube player ] At 13:11, 6502 at 8 Mhz running KG3D texture-mapped 3D game is impressive for an 8 Mhz CPU (effectively 16 Mhz due to double rate processing). "The 8-bit Guy" warns against straight Mhz comparisons. 6502's double-rate characteristics have been assimilated into AMD. Last edited by hammer; 08 April 2024 at 02:21. |
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08 April 2024, 01:34 | #3474 | |
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5 bit planes: first I’d compute the Y coordinate start address, this is similar in both scenarios, imagining the hardware would discard up to N bits (final columns) in packed mode. Then for planar I’d need to compute the bit modulo 8 (3), then divide by 8 to find the offset from the start of the row, then perform TEN accesses to memory - read with a mask - just to change one single colour. Ok on a 68020 I could leverage on bfset operations making it fairly easier and faster, but I was thinking of a 68000 ECS Amiga and of the blitter too. Packed chunky 5 bits: similarly I’d compute the start of a row and the I’d need to divide the X coordinate by the number of planes (in this case 5), to get the initial bit, and then change 5 bits with two accesses to memory: read the resulting word, AND with a mask, OR the five changed bits with the value 5 (colour red) in one go. In the worst case the bits would spawn two bytes, so two extra accesses (as the 68000 dislikes word access to odd addresses), but most of the times it would be one read + one write. I could do another memory access to get the right value of the mask from a table. Three to five memory accesses against 10! I understand this algorithm changes based on the display depth, but it’s basically always a lot less bandwidth, even for a blitter. If it was implemented in the Amiga 1000, we’d have had a lot more games running in 1 frame and 32 colours, something quite hard to achieve with the standard bitplane architecture that we got. Edit: oh and a clever chipset like Amiga’s could’ve used some optimisations, like discarding the extra bit that would go to an odd address and keep all accesses aligned, at the expense of some ram. We’re talking about one bit every three pixels… for a 320x200 display that’s less than 3k of memory wasted. The AGA copper wastes a lot of memory (and bandwidth…) just to define a 24bit palette. With this I’m not saying the original design was bad, as someone said most likely they started with a flight simulator in mind, and kept what was on the chip adapted to bit planes. Last edited by emiespo; 08 April 2024 at 01:45. Reason: Added more info |
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08 April 2024, 01:49 | #3475 | |
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This Amiga clone didn't use Commodore's Gayle and Budgie. Access incorporates the core Amiga chips only: Alice, Paula, Lisa, and 8520 CIAs. Commodore wasn't in the business of selling Amiga chipsets for Amiga clones. |
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08 April 2024, 02:25 | #3476 | |
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Pilotwings didn't use SuperFX, it's effectively a game tech demo for SNES's Mode 7. NES's Mode 7 and Mode 7 Direct Color supports packed pixels. Brian the Lion has shown some Mode 7-like effects. Last edited by hammer; 08 April 2024 at 02:33. |
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08 April 2024, 02:46 | #3477 |
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08 April 2024, 03:14 | #3478 |
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08 April 2024, 03:29 | #3479 | |||
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Jay Miner chose bitplanes for one simple reason - he could make a circuit that did 1 bitplane and apply it to as many as he wanted without a lot of tricky logic. And he didn't have any fancy HDL tools to create and debug it. To test the design he had to build the circuit on a wire-wrap board. These photos of the Lorraine prototype give you an idea of what a massive undertaking that was. If you've ever built logic circuits this way you will appreciate the effort that went into it. I've done a few, but I would never attempt something this large and complex. The Blitter had to work in bitplane mode for doing 1 bitplane anyway, but guess how much extra circuitry you need to do multiple bitplanes? That's right, nothing. So you design your single bitplane blitter and that's it! Then to get more colors you just stack up multiple identical 1 bitplane display boards, and feed their output into the LUT. Perhaps even separate them into 2 groups, each generating its own display (dual playfield). And the blitter doesn't have to know anything about this. But hey, perhaps you are right and it wouldn't be any more complex. Unfortunately - unlike today's armchair engineers - Jay Miner didn't think to do all it in packed pixel mode. Strangely nobody else did either. I guess they just weren't as smart as Amiga fans of today - probably due to all that tetraethyl lead they were breathing in back then. Quote:
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08 April 2024, 04:33 | #3480 |
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