LUCAS & FRANCES Boards, PAL Code & PCB Masks

[sanjyuubi]

Can someone post LUCAS schematics in windows edible format? KAIs links doesnt work.

BTW, do Somebody knows how exactly 68000 timings have to be recreated in PLD? I'm talking about propagation times of signals after clock edges.

[Kai]

Hey, sorry, that FTP disappeared on me, i'll try and re-host it somewhere.

[Nikodem]

Kai, could you re-up the links with the documentation. I'm seeking some projects for my A500 and this looks promising.

[klx300r]

well I was lucky enough to find a LUCAS board locally but won't be able to test it until my A1000 is back up in a month or so. Anyone else have one up & running yet ?

[quarkx]

You might want to drop a line to Craig at Amitrix. He has a few of these cards running fine with both the Lucas and Francis boards.

[klx300r]

Originally Posted by quarkx

You might want to drop a line to Craig at Amitrix. He has a few of these cards running fine with both the Lucas and Francis boards.

will do, thanks

Any updates on the Eagle files for this redo of the Lucas/Frances project?
A lot of the potential signal integrity issues on the 4 layer PCB can resolved by adding a series termination resistors@ 22 to 33ohms (i.e. high speed edge rate nets such 68020 CPU bus, PLD, CLocks, etc ...) and eliminating any long stubs on the transmission lines/routes.

[pandy71]

Originally Posted by jkonstan

Any updates on the Eagle files for this redo of the Lucas/Frances project?
A lot of the potential signal integrity issues on the 4 layer PCB can resolved by adding a series termination resistors@ 22 to 33ohms (i.e. high speed edge rate nets such 68020 CPU bus, PLD, CLocks, etc ...) and eliminating any long stubs on the transmission lines/routes.

i've started Eagle 2 layer version but currently this is suspended - at this point i still consider to restart project with free an open sourced kicad (libraries from Eagle for kicad are available)

Kicad with Eagle libraries would be fine.
You may want to use 4layers on the PCB(s) due to power and Signal integrity issues that will likely occur on a 2layer PCB.

[pandy71]

Originally Posted by jkonstan

Kicad with Eagle libraries would be fine.
You may want to use 4layers on the PCB(s) due to power and Signal integrity issues that will likely occur on a 2layer PCB.

4 layers imply ordering PCB even for pre-proto stage - it is to expensive IMHO
So i decided to if this is possible to kept 2 layer PCB idea.
This should be possible but probably manual routing is required.

[Kai]

Heyo! Sorry to resurrect this thread from the dead - haven't logged in in a lonnnnnnng time (sorry!), major personal life upheaval here

For anyone that's still interested, i'm more than happy to try and upload the stuff from earlier - the FTP where i was hosting went bye bye - when i do, i'll amend the first post

[chaos]

Thanks, didn't even know about this until now I'll definitely check it out!

[kipper2k]

4 layer PCBs are not that expensive nowadays. If you want to do this project i think you need to verify all components are still available first and if so, think about a group buy to reduce the costs

[pandy71]

Originally Posted by kipper2k

4 layer PCBs are not that expensive nowadays. If you want to do this project i think you need to verify all components are still available first and if so, think about a group buy to reduce the costs

Yep, after some time i also voting for 4 layer PCB - thanks to Smart-Prototyping, 4 layer is no longer insanely expensive.
But also PAL need to be addressed - preferred is 1 CPLD.

[Kai]

I can have a word with my friend Geoff about that, actually. I mentioned the issue to him before, combining the PAL's into a single CPLD/FPGA and he says it should be simple enough. That being said, all the PAL's are still available. Would just need a supply of 68020's - i presume EC020's would also work, as they're just 24-bit bus instead of the full 32-bit, right?

[pandy71]

Originally Posted by Kai

I can have a word with my friend Geoff about that, actually. I mentioned the issue to him before, combining the PAL's into a single CPLD/FPGA and he says it should be simple enough. That being said, all the PAL's are still available. Would just need a supply of 68020's - i presume EC020's would also work, as they're just 24-bit bus instead of the full 32-bit, right?

I would say, single IC make PCB routing simpler, second PAL (GAL) require specialized programmer devices - for example personally chasing from long time algorithm to program AMD PALCE series and after log searching have no success - thus some modern, ISP devices will be probably better than outdated GAL - ABEL GAL description is not complex to convert - it is only time consuming and i don't feel secure enough to do translation only based on code.

Yes, 68EC020 is OK, address bus limited to 24 bits but remain part should be straightforward and compatible with full 68020.

[Kai]

The reason i mention the EC040 is because of the pinout, its easier for routing, for one, and secondly, they're easier to source. I don't mind doing one PCB layout for a QFP EC020 and another for either a PGA/PLCC full 020.

[pandy71]

Originally Posted by Kai

its easier for routing, for one

This seem to be most important: availability and price (and this is also why idea to create CPU in FPGA sounds very tempting).

[Kai]

Okay - for simplicity sake, regarding the schematic (16 extra lines isn't enough of a saving, really) i'll discount the EC020. Will be looking instead at full 020 or 030, with a 68882. From this point on, those will be the only two options.

For the glue logic - PAL's will be replaced with a single CPLD, specifically this one: http://uk.mouser.com/ProductDetail/A...2fe555v6LKo%3d

As Pandy has already mentioned, takes up far less space on the board, and makes routing a lot easier.

Now it's just a case of - who wants QFP vs PGA? QFP takes up less space and generate less heat, but makes it a bit harder for someone to build one themselves, although not impossible - the PGA would make it more enthusiast friendly. As for the rest - would you want SMT components or regular? I'm a little on the fence myself, i see the benefits of SMT, but i'd rather have something thats more accessible.

Finally - i was considering adding in a 32 to 128kb cache for the '030 model as per the Macintosh IIci - although i don't know if the MMU in the 030 is enough, or i'd need a cache controller - maybe pie in the sky, but i like the idea.

Thoughts/opinons?

[kipper2k]

Originally Posted by Kai

Okay - for simplicity sake, regarding the schematic (16 extra lines isn't enough of a saving, really) i'll discount the EC020. Will be looking instead at full 020 or 030, with a 68882. From this point on, those will be the only two options.

For the glue logic - PAL's will be replaced with a single CPLD, specifically this one: http://uk.mouser.com/ProductDetail/A...2fe555v6LKo%3d

As Pandy has already mentioned, takes up far less space on the board, and makes routing a lot easier.

Now it's just a case of - who wants QFP vs PGA? QFP takes up less space and generate less heat, but makes it a bit harder for someone to build one themselves, although not impossible - the PGA would make it more enthusiast friendly. As for the rest - would you want SMT components or regular? I'm a little on the fence myself, i see the benefits of SMT, but i'd rather have something thats more accessible.

Finally - i was considering adding in a 32 to 128kb cache for the '030 model as per the Macintosh IIci - although i don't know if the MMU in the 030 is enough, or i'd need a cache controller - maybe pie in the sky, but i like the idea.

Thoughts/opinons?

That Altera CPLD is pretty easy to solder, just need to soak it in flux to reduce possibility of bridges. I use solder soaked braid to actually solder them and it works very well. SMT where possible is the way to go on a 2 layer board, trying to keep the resistors and caps to a minimum 0805 size