Zorro III Bus Specifications wanted

[tnt23]

I don't quite catch the idea, why would one clone Buster?

[wawa]

@tnt23:
http://www.a1k.org/forum/showpost.ph...1&postcount=18
under this link calculates m. boehmer, author of the deneb zorro usb-card the maximal theoretical throughtput of z3 bus.

.... pro 32bit (access) 30ns Adress-Setup, 30ns Address-Hold, 20ns DOE-to-/DS und 150ns Data Phase. [...] summa summarum 230ns, [...] (+) intercycle gap of ca. 100ns, [...] > 32bit Zugriff (ideally) 330ns...

...11.6MB/s

bernd roesch has told me once his merlin provides even 14mb/s busspeed, cannot verify this. my mediator (with voodoo3) and deneb remain within 7mb/s effective data throughput in an a4k.

[zipper]

PicassoIV 10-11 MB/s, CV64 is probaly the fastest on Zorro, 16-18 MB/s IIRC. Theoretical max should equal PCI but it's theory...

[wawa]

picasso is considered quite compatible for what i ve heard, probably just working along the z3 specs it reaches maximal throughput. cv64 must be pulling some tricks to get that result. i do not know what tricks, yet less i would understand, but i recall it is being considered a problem source by individual computers and e3b. i could provide some hints by them if i wíll find a while to do that.

[aperez]

Originally Posted by tnt23

My A3000's Zorro bus now carries Cybervision64, Deneb and Buddha on top of that. (Although Buddha is not a Z3 card.) Not bad for a 'stillborn' bus!

Agreed,it is impressive! As is your work. Will it be zorro II compatible? Do you have any plans to release the layout? Which FPGA have you chosen?

[tnt23]

Originally Posted by aperez

Agreed,it is impressive! As is your work. Will it be zorro II compatible? Do you have any plans to release the layout? Which FPGA have you chosen?

I haven't got all signals necessary for Z2 routed into the FPGA, like the clocks. A rework on schematics and PCB layout will be needed for that. Adding Z2 compatibility will then be a matter of rewriting the FPGA firmware.

The FPGA is 208-pin QFP chip from Cyclone II family. It is not 5v tolerant, hence the Quickswitches.

Releasing the PCB layout is quite possible. I doubt it will be of great interest as it only supports one memory chip (and hasn't been verified against all sorts of errors and mistakes).

[aperez]

Originally Posted by wawa

nice try. i wonder where all that inspiration comes from.. as alexh said there are plenty busters of all sorts flying around. the only reason for a replacement would be to iron out the long known bugs of these chips that have been mostly worked around already anyway. also how do you want to reverse ingeneer? or is there documentation available?

Nice try? So much for encouragement...

I put a good five or six hours into the reverse engineering process on my A3000D last night, using a BugKatcher, which is an 84-pin PLCC device that plugs into a PLCC sockets and gives easy access to all of the pins for diagnostic purposes. Here's a photo of my Buster in the bugKatcher:



High-res photo of the same thing is viewable at http://farm5.static.flickr.com/4071/...8bfb7819_b.jpg

[wawa]

Originally Posted by aperez

Nice try? So much for encouragement...

I put a good five or six hours into the reverse engineering process on my A3000D last night, using a BugKatcher, which is an 84-pin PLCC device that plugs into a PLCC sockets and gives easy access to all of the pins for diagnostic purposes. Here's a photo of my Buster in the bugKatcher:



High-res photo of the same thing is viewable at http://farm5.static.flickr.com/4071/...8bfb7819_b.jpg

very well. any results? i mean except of a photo..

( i mean at least there is a proof that it fits)

[Shadowfire]

Usually, by the time a hardware hacker decides to spend the dosh to have a professional PCB made, they are pretty sure they have a good chance of getting it working.

[tnt23]

Originally Posted by Shadowfire

Usually, by the time a hardware hacker decides to spend the dosh to have a professional PCB made, they are pretty sure they have a good chance of getting it working.

Yet when you power the thing up for the first time and it works, it feels just like miracle for me every time

[ Show youtube player ]

[DarrenHD]

Originally Posted by tnt23

Yet when you power the thing up for the first time and it works, it feels just like miracle for me every time

[ Show youtube player ]

wow!! it's alive awesome progress!! anything else you can tell us about the board? How much memory can it have?

[alexh]

Plug it in Let out the Magic Smoke.

Nice job, you seem committed to producing something which is very cool.

[tnt23]

Originally Posted by DarrenHD

wow!! it's alive awesome progress!! anything else you can tell us about the board? How much memory can it have?

The FPGA seems to be quite happy with power supplies and configuration and programming pins. Currently it is powered from a separate 5v source. The code is mostly blinking the LEDS, and its Autoconfig part is slowly coming to life, according to functional simulation reports. (And then there is timing simulation to be done.) After Autoconfig is working, I'll solder the Quickswitches and cram the board into friend's A4000.

This PCB was intended to be a test board, so it can carry only one SDRAM chip. I was going to use the same memory IC that Altera's DE1 development board has, 8 megabytes in 16-bit words. Address lines should allow for bigger memory organizations, like 16, 32 and 64 megabyte chips. More chip selects can be added later, as well as another memory chip.

There are also 7 free GPIO pins available as a 2.54mm header strip, can be used for debugging or something else.

[alexh]

Originally Posted by tnt23

I'll cram the board into friend's A4000.

Wow that is a good friend

[FrenchShark]

Originally Posted by tnt23

The FPGA seems to be quite happy with power supplies and configuration and programming pins. Currently it is powered from a separate 5v source. The code is mostly blinking the LEDS, and its Autoconfig part is slowly coming to life, according to functional simulation reports. (And then there is timing simulation to be done.) After Autoconfig is working, I'll solder the Quickswitches and cram the board into friend's A4000.

This PCB was intended to be a test board, so it can carry only one SDRAM chip. I was going to use the same memory IC that Altera's DE1 development board has, 8 megabytes in 16-bit words. Address lines should allow for bigger memory organizations, like 16, 32 and 64 megabyte chips. More chip selects can be added later, as well as another memory chip.

There are also 7 free GPIO pins available as a 2.54mm header strip, can be used for debugging or something else.

Good job !
Welcome to the world of FPGAs and SDRAMs.
The toughest part in the development is using TimeQuest and getting the external I/Os timings right.
If you need some help on that part, just PM me.

Regards,

Frederic

Originally Posted by tnt23

Yet when you power the thing up for the first time and it works, it feels just like miracle for me every time

[ Show youtube player ]

The same here.

I prefer spending more time reading datasheets and double-checking the layout than pulling my hair on a non-working PCB.

I also check all the voltage rails before soldering the expensive components.

Regards,

Frederic

Originally Posted by tnt23

The FPGA seems to be quite happy with power supplies and configuration and programming pins. Currently it is powered from a separate 5v source. The code is mostly blinking the LEDS, and its Autoconfig part is slowly coming to life, according to functional simulation reports. (And then there is timing simulation to be done.) After Autoconfig is working, I'll solder the Quickswitches and cram the board into friend's A4000.

This PCB was intended to be a test board, so it can carry only one SDRAM chip. I was going to use the same memory IC that Altera's DE1 development board has, 8 megabytes in 16-bit words. Address lines should allow for bigger memory organizations, like 16, 32 and 64 megabyte chips. More chip selects can be added later, as well as another memory chip.

There are also 7 free GPIO pins available as a 2.54mm header strip, can be used for debugging or something else.

I do not see an SPI flash on the PCB. You cannot get the board working in standalone mode (without a USB blaster attached)

Regards,

Frederic

[tnt23]

Originally Posted by alexh

Wow that is a good friend

That's what friends are for! (He's got another one, just in case )

[tnt23]

Originally Posted by FrenchShark

Good job !
Welcome to the world of FPGAs and SDRAMs.
The toughest part in the development is using TimeQuest and getting the external I/Os timings right.
If you need some help on that part, just PM me.

Thanks Frederic. The SDRAM module has been tested on Altera DE1 at 50MHz and 100MHz so I hardly expect any difficulties here. Except maybe problems with clock lines being too short and missing resistors in series. Haven't dealt with TimeQuest yet, mostly spend my time in classic Simulator.

The same here.

I prefer spending more time reading datasheets and double-checking the layout than pulling my hair on a non-working PCB.

I also check all the voltage rails before soldering the expensive components.

That sorta goes without saying Double-checking the layout for me means I almost immediately find something worth enhancing; then a trace to be redone, and a couple of components to be moved here and there. Cannot stare at the layout forever, want to fiddle with real hardware!

I do not see an SPI flash on the PCB. You cannot get the board working in standalone mode (without a USB blaster attached)

At the top left corner of the board, right under the JTAG connector, an SO-8 EP1C configuration flash will be soldered. It cannot be programmed via JTAG directly as it is not on the chain, but there is a way of programming it through FPGA. I've again got an appnote on that somewhere.

[Shadowfire]

Yep. Spent about a week working on the first layout of my IDE controller, and found about a dozen mistakes/improvements after it was made.

Still, you are right, you do need to eventually settle on something, or it will never get done.

[wawa]

@shadowfire:

Originally Posted by Shadowfire

Usually, by the time a hardware hacker decides to spend the dosh to have a professional PCB made, they are pretty sure they have a good chance of getting it working.

i wasnt reffering to tnt32.

@tnt32: very cool!

[Shadowfire]

You've glossed over the lack of series resistors on the proto board.

The series resistors are almost certainly there to reduce the slew rate (and therefore, the the over- and under-shoot) of the I/O lines. You want to be real careful about this, since the Cyclone devices have very specific tolerances about how much over and undershoot they can take without degrading/dying, discussed in the data sheets.

Directly related to this, is the fact that Zorro 2/3 was never conceived with operating with the kinds of slew rates these FPGAs will put out. So, you may wish to check on over/undershoot on the Zorro bus as well, even though you have quickswitches there.